diff --git a/InstructionSets/68k/Decoder.cpp b/InstructionSets/68k/Decoder.cpp
index 5877de98d..ec06620ed 100644
--- a/InstructionSets/68k/Decoder.cpp
+++ b/InstructionSets/68k/Decoder.cpp
@@ -142,7 +142,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 //		case ANDIb:		case ANDIl:		case ANDIw:
 		case SUBIb:		case SUBIl:		case SUBIw:
 		case ADDIb:		case ADDIl:		case ADDIw:
-//		case CMPIb:		case CMPIl:		case CMPIw:
 			switch(original.mode<1>()) {
 				default: return original;
 
@@ -154,6 +153,23 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 					return Preinstruction();
 			}
 
+		case CMPIb:		case CMPIl:		case CMPIw:
+			switch(original.mode<1>()) {
+				default: return original;
+
+				case AddressingMode::ProgramCounterIndirectWithDisplacement:
+				case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
+					if constexpr (model >= Model::M68010) {
+						return original;
+					}
+					[[fallthrough]];
+
+				case AddressingMode::AddressRegisterDirect:
+				case AddressingMode::ImmediateData:
+				case AddressingMode::None:
+					return Preinstruction();
+			}
+
 		// ADD, SUB, MOVE, MOVEA
 		case OpT(Operation::ADDb):		case OpT(Operation::ADDw):	case OpT(Operation::ADDl):
 		case OpT(Operation::SUBb):		case OpT(Operation::SUBw):	case OpT(Operation::SUBl):
@@ -251,19 +267,41 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 				case AddressingMode::ImmediateData:
 					return Preinstruction();
 			}
-//
-//		case BCHGI:	case BSETI:	case BCLRI:
-//			switch(original.mode<1>()) {
-//				default: return original;
-//
-//				case AddressingMode::None:
-//				case AddressingMode::AddressRegisterDirect:
-//				case AddressingMode::ProgramCounterIndirectWithDisplacement:
-//				case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
-//				case AddressingMode::ImmediateData:
-//					return Preinstruction();
-//			}
-}
+
+		case OpT(Operation::TSTb):	case OpT(Operation::TSTw):	case OpT(Operation::TSTl):
+			switch(original.mode<0>()) {
+				default: return original;
+
+				case AddressingMode::AddressRegisterDirect:
+					if constexpr (op == OpT(Operation::TSTb)) {
+						return Preinstruction();
+					}
+					[[fallthrough]];
+
+				case AddressingMode::ImmediateData:
+					if constexpr (model < Model::M68020) {
+						return Preinstruction();
+					}
+					return original;
+
+				case AddressingMode::ProgramCounterIndirectWithDisplacement:
+				case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
+					if constexpr (model >= Model::M68010) {
+						return original;
+					}
+					[[fallthrough]];
+				case AddressingMode::None:
+					return Preinstruction();
+			}
+
+		case OpT(Operation::CMPAw):	case OpT(Operation::CMPAl):
+			switch(original.mode<0>()) {
+				default: return original;
+
+				case AddressingMode::None:
+					return Preinstruction();
+			}
+	}
 }
 
 /// Decodes the fields within an instruction and constructs a `Preinstruction`, given that the operation has already been
diff --git a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
index 325c9647e..94d1c7feb 100644
--- a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm	
@@ -138,6 +138,17 @@ template <int index> NSString *operand(Preinstruction instruction) {
 			case Operation::BCHG:	instruction = @"BCHG";	break;
 			case Operation::BSET:	instruction = @"BSET";	break;
 
+			case Operation::CMPb:	instruction = @"CMP.b";	break;
+			case Operation::CMPw:	instruction = @"CMP.w";	break;
+			case Operation::CMPl:	instruction = @"CMP.l";	break;
+
+			case Operation::CMPAw:	instruction = @"CMPA.w";	break;
+			case Operation::CMPAl:	instruction = @"CMPA.l";	break;
+
+			case Operation::TSTb:	instruction = @"TST.b";	break;
+			case Operation::TSTw:	instruction = @"TST.w";	break;
+			case Operation::TSTl:	instruction = @"TST.l";	break;
+
 			// For now, skip any unmapped operations.
 			default: continue;
 		}