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Attempt BTST, BCHG, BCLR and BSET.

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This commit is contained in:
Thomas Harte 2022-05-20 12:58:45 -04:00
parent 6d7ec07216
commit 81431a5453
3 changed files with 73 additions and 2 deletions
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2
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@ -156,7 +156,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
_fileSet = [NSSet setWithArray:@[
// @"btst_bchg_bclr_bset.json",
@"btst_bchg_bclr_bset.json",
// Below this line are passing tests.
@"abcd_sbcd.json",

67
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -98,6 +98,9 @@ enum ExecutionState: int {
Bcc_w_branch_not_taken,
BSR,
BCHG_BSET_Dn,
BCLR_Dn,
};
// MARK: - The state machine.
@ -536,6 +539,43 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(BSRb, perform_state_ = BSR);
StdCASE(BSRw, perform_state_ = BSR);
StdCASE(BTST, {
switch(instruction_.mode(1)) {
default:
perform_state_ = Perform_np;
break;
case Mode::DataRegisterDirect:
case Mode::ImmediateData:
perform_state_ = Perform_np_n;
break;
}
});
Duplicate(BCHG, BSET)
StdCASE(BSET, {
switch(instruction_.mode(1)) {
default:
perform_state_ = Perform_np;
break;
case Mode::DataRegisterDirect:
case Mode::ImmediateData:
perform_state_ = BCHG_BSET_Dn;
break;
}
});
StdCASE(BCLR, {
switch(instruction_.mode(1)) {
default:
perform_state_ = Perform_np;
break;
case Mode::DataRegisterDirect:
case Mode::ImmediateData:
perform_state_ = BCLR_Dn;
break;
}
});
default:
assert(false);
}
@ -1213,6 +1253,29 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); // np
MoveToState(Decode);
//
// BSET, BCHG, BCLR
//
BeginState(BCHG_BSET_Dn):
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
IdleBus(1 + did_bit_op_high_);
registers_[instruction_.reg(1)] = operand_[1];
MoveToState(Decode);
BeginState(BCLR_Dn):
InstructionSet::M68k::perform<
InstructionSet::M68k::Model::M68000,
ProcessorBase,
InstructionSet::M68k::Operation::BCLR
>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
IdleBus(2 + did_bit_op_high_);
registers_[instruction_.reg(1)] = operand_[1];
MoveToState(Decode);
//
// Various states TODO.
//
@ -1295,6 +1358,10 @@ void ProcessorBase::bsr(uint32_t offset) {
program_counter_.l = instruction_address_.l + offset + 2;
}
void ProcessorBase::did_bit_op(int bit_position) {
did_bit_op_high_ = bit_position > 15;
}
// MARK: - External state.
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>

6
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
View File

@ -87,6 +87,10 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
/// Transient storage for exception processing.
SlicedInt16 captured_status_;
/// An internal flag used during BCHG, BSET and BCLR processing to
/// determine total operation cost.
bool did_bit_op_high_ = false;
// Flow controller... all TODO.
using Preinstruction = InstructionSet::M68k::Preinstruction;
@ -106,7 +110,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
inline void did_shift(int) {}
template <bool did_overflow> void did_divu(uint32_t, uint32_t) {}
template <bool did_overflow> void did_divs(int32_t, int32_t) {}
inline void did_bit_op(int) {}
inline void did_bit_op(int);
inline void did_update_status();
template <typename IntT> void complete_bcc(bool, IntT);
inline void complete_dbcc(bool, bool, int16_t);