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Resolve various test-case warnings.

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This commit is contained in:
Thomas Harte 2020-09-27 15:10:29 -04:00
parent 5449e90b34
commit 8641494809
10 changed files with 14 additions and 21 deletions
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4
OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj
View File

@ -4025,7 +4025,7 @@
isa = PBXProject;
attributes = {
LastSwiftUpdateCheck = 0700;
LastUpgradeCheck = 1130;
LastUpgradeCheck = 1200;
ORGANIZATIONNAME = "Thomas Harte";
TargetAttributes = {
4B055A691FAE763F0060FFFF = {
@ -5170,6 +5170,7 @@
CLANG_WARN_OBJC_IMPLICIT_RETAIN_SELF = YES;
CLANG_WARN_OBJC_LITERAL_CONVERSION = YES;
CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
CLANG_WARN_QUOTED_INCLUDE_IN_FRAMEWORK_HEADER = YES;
CLANG_WARN_RANGE_LOOP_ANALYSIS = YES;
CLANG_WARN_STRICT_PROTOTYPES = YES;
CLANG_WARN_SUSPICIOUS_MOVE = YES;
@ -5228,6 +5229,7 @@
CLANG_WARN_OBJC_IMPLICIT_RETAIN_SELF = YES;
CLANG_WARN_OBJC_LITERAL_CONVERSION = YES;
CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
CLANG_WARN_QUOTED_INCLUDE_IN_FRAMEWORK_HEADER = YES;
CLANG_WARN_RANGE_LOOP_ANALYSIS = YES;
CLANG_WARN_STRICT_PROTOTYPES = YES;
CLANG_WARN_SUSPICIOUS_MOVE = YES;

2
OSBindings/Mac/Clock Signal.xcodeproj/xcshareddata/xcschemes/Clock Signal Kiosk.xcscheme
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Scheme
LastUpgradeVersion = "1130"
LastUpgradeVersion = "1200"
version = "1.3">
<BuildAction
parallelizeBuildables = "YES"

2
OSBindings/Mac/Clock Signal.xcodeproj/xcshareddata/xcschemes/Clock Signal.xcscheme
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Scheme
LastUpgradeVersion = "1130"
LastUpgradeVersion = "1200"
version = "1.3">
<BuildAction
parallelizeBuildables = "YES"

11
OSBindings/Mac/Clock Signal.xcodeproj/xcshareddata/xcschemes/Clock SignalTests.xcscheme
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Scheme
LastUpgradeVersion = "1130"
LastUpgradeVersion = "1200"
version = "1.3">
<BuildAction
parallelizeBuildables = "YES"
@ -51,15 +51,6 @@
savedToolIdentifier = ""
useCustomWorkingDirectory = "NO"
debugDocumentVersioning = "YES">
<MacroExpansion>
<BuildableReference
BuildableIdentifier = "primary"
BlueprintIdentifier = "4BB73E9D1B587A5100552FC2"
BuildableName = "Clock Signal.app"
BlueprintName = "Clock Signal"
ReferencedContainer = "container:Clock Signal.xcodeproj">
</BuildableReference>
</MacroExpansion>
</ProfileAction>
<AnalyzeAction
buildConfiguration = "Debug">

2
OSBindings/Mac/Clock SignalTests/6502TimingTests.swift
View File

@ -200,7 +200,7 @@ class MOS6502TimingTests: XCTestCase, CSTestMachineTrapHandler {
func runTest(_ code: [UInt8], expectedRunLength: UInt32) {
machine.trapHandler = self
let immediateCode = Data(bytes: UnsafePointer<UInt8>(code), count: code.count)
let immediateCode = Data(code)
machine.setData(immediateCode, atAddress: 0x200)
machine.addTrapAddress(UInt16(0x200 + code.count))
machine.setValue(0x00, forAddress: 0x0000)

4
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@ -91,12 +91,12 @@
Test68000() : processor(*this) {
}
void will_perform(uint32_t address, uint16_t opcode) {
void will_perform(uint32_t, uint16_t) {
--instructions_remaining_;
if(!instructions_remaining_) comparitor();
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
using Microcycle = CPU::MC68000::Microcycle;
if(cycle.data_select_active()) {
cycle.apply(&ram[cycle.host_endian_byte_address()]);

2
OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
View File

@ -36,7 +36,7 @@ class EmuTOS: public ComparativeBusHandler {
return m68000_.get_state();
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
const uint32_t address = cycle.word_address();
uint32_t word_address = address;

2
OSBindings/Mac/Clock SignalTests/QLTests.mm
View File

@ -39,7 +39,7 @@ class QL: public ComparativeBusHandler {
return m68000_.get_state();
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
const uint32_t address = cycle.word_address();
uint32_t word_address = address;

4
OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp
View File

@ -48,7 +48,7 @@ class RAM68000: public CPU::MC68000::BusHandler {
ram_[1] = sp & 0xffff;
}
void will_perform(uint32_t address, uint16_t opcode) {
void will_perform(uint32_t, uint16_t) {
--instructions_remaining_;
}
@ -80,7 +80,7 @@ class RAM68000: public CPU::MC68000::BusHandler {
return &ram_[(address >> 1) % ram_.size()];
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
const uint32_t word_address = cycle.word_address();
if(instructions_remaining_) duration_ += cycle.length;

2
Processors/Z80/AllRAM/Z80AllRAM.hpp
View File

@ -29,7 +29,7 @@ class AllRAMProcessor:
}
struct PortAccessDelegate {
virtual uint8_t z80_all_ram_processor_input(uint16_t port) { return 0xff; }
virtual uint8_t z80_all_ram_processor_input(uint16_t) { return 0xff; }
};
inline void set_port_access_delegate(PortAccessDelegate *delegate) {
port_delegate_ = delegate;