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Improve documentation, pin down read/write times.

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This commit is contained in:
Thomas Harte 2021-04-01 12:38:58 -04:00
parent 687c05365e
commit 87317f5673
2 changed files with 16 additions and 3 deletions
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10
Machines/Sinclair/ZXSpectrum/Video.hpp
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@ -88,14 +88,20 @@ template <VideoTiming timing> class Video {
.cycles_per_line = 228 * 2,
.lines_per_frame = 311,
.interrupt_time = 56542 * 2,
// i.e. video fetching begins five cycles after the start of the
// contended memory pattern below; that should put a clear two
// cycles between a Z80 access and the first video fetch.
.contention_leadin = 5 * 2,
.contention_duration = 129 * 2,
// i.e. interrupt is first signalled
// 311*228 - 5 - 56543 = 14364 cycles before the beginning of
// contended accesses.
//
// (which, as above, include a bit of guesswork as to the meaning of
// 'time since interrupt' in the commonly-cited documentation)
.interrupt_time = 56543 * 2,
.delays = {
2, 1,
0, 0,

9
Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp
View File

@ -206,7 +206,11 @@ template<Model model> class ConcreteMachine:
// the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended
// timings am I now learning what happens with MREQ during extended read/write bus cycles
// (i.e. those longer than 3 cycles)
advance(cycle.length);
if(cycle.length > HalfCycles(5)) {
advance(HalfCycles(5));
} else {
advance(cycle.length);
}
switch(cycle.operation) {
default: break;
@ -364,6 +368,9 @@ template<Model model> class ConcreteMachine:
break;
}
if(cycle.length > HalfCycles(5)) {
advance(cycle.length - HalfCycles(5));
}
return HalfCycles(0);
}