From 87317f5673a6a943b6a591a1ec7225e7db80f6bf Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Thu, 1 Apr 2021 12:38:58 -0400 Subject: [PATCH] Improve documentation, pin down read/write times. --- Machines/Sinclair/ZXSpectrum/Video.hpp | 10 ++++++++-- Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp | 9 ++++++++- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/Machines/Sinclair/ZXSpectrum/Video.hpp b/Machines/Sinclair/ZXSpectrum/Video.hpp index 2c03545ec..49d81325c 100644 --- a/Machines/Sinclair/ZXSpectrum/Video.hpp +++ b/Machines/Sinclair/ZXSpectrum/Video.hpp @@ -88,14 +88,20 @@ template class Video { .cycles_per_line = 228 * 2, .lines_per_frame = 311, - .interrupt_time = 56542 * 2, - // i.e. video fetching begins five cycles after the start of the // contended memory pattern below; that should put a clear two // cycles between a Z80 access and the first video fetch. .contention_leadin = 5 * 2, .contention_duration = 129 * 2, + // i.e. interrupt is first signalled + // 311*228 - 5 - 56543 = 14364 cycles before the beginning of + // contended accesses. + // + // (which, as above, include a bit of guesswork as to the meaning of + // 'time since interrupt' in the commonly-cited documentation) + .interrupt_time = 56543 * 2, + .delays = { 2, 1, 0, 0, diff --git a/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp b/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp index d924a0144..2d4050771 100644 --- a/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp +++ b/Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp @@ -206,7 +206,11 @@ template class ConcreteMachine: // the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended // timings am I now learning what happens with MREQ during extended read/write bus cycles // (i.e. those longer than 3 cycles) - advance(cycle.length); + if(cycle.length > HalfCycles(5)) { + advance(HalfCycles(5)); + } else { + advance(cycle.length); + } switch(cycle.operation) { default: break; @@ -364,6 +368,9 @@ template class ConcreteMachine: break; } + if(cycle.length > HalfCycles(5)) { + advance(cycle.length - HalfCycles(5)); + } return HalfCycles(0); }