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Corrects DJNZ memptr behaviour.

This commit is contained in:
Thomas Harte 2020-02-26 21:42:31 -05:00
parent da6d5e2e24
commit 8878396339
3 changed files with 3 additions and 4 deletions

View File

@ -172,7 +172,7 @@ class FUSETests: XCTestCase {
let name = itemDictionary["name"] as! String let name = itemDictionary["name"] as! String
// if name != "01" { // if name != "10" {
// continue; // continue;
// } // }
// print("\(name)") // print("\(name)")

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@ -181,7 +181,6 @@ template < class T,
case MicroOp::DJNZ: case MicroOp::DJNZ:
bc_.halves.high--; bc_.halves.high--;
if(!bc_.halves.high) { if(!bc_.halves.high) {
memptr_.full = pc_.full;
advance_operation(); advance_operation();
} }
break; break;
@ -873,7 +872,7 @@ template < class T,
break; break;
case MicroOp::CalculateIndexAddress: case MicroOp::CalculateIndexAddress:
memptr_.full = static_cast<uint16_t>(*static_cast<uint16_t *>(operation->source) + (int8_t)temp8_); memptr_.full = static_cast<uint16_t>(*static_cast<uint16_t *>(operation->source) + int8_t(temp8_));
break; break;
case MicroOp::SetAddrAMemptr: case MicroOp::SetAddrAMemptr:

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@ -371,7 +371,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
DEC_INC_DEC_LD(bc_, bc_.halves.low), DEC_INC_DEC_LD(bc_, bc_.halves.low),
/* 0x0f RRCA */ StdInstr({MicroOp::RRCA}), /* 0x0f RRCA */ StdInstr({MicroOp::RRCA}),
/* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::Move16, &pc_.full, &memptr_.full}, {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), /* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
/* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)), /* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)),
/* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)), /* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)),