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Corrects DJNZ memptr behaviour.
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parent
da6d5e2e24
commit
8878396339
@ -172,7 +172,7 @@ class FUSETests: XCTestCase {
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let name = itemDictionary["name"] as! String
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let name = itemDictionary["name"] as! String
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// if name != "01" {
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// if name != "10" {
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// continue;
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// continue;
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// }
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// }
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// print("\(name)")
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// print("\(name)")
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@ -181,7 +181,6 @@ template < class T,
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case MicroOp::DJNZ:
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case MicroOp::DJNZ:
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bc_.halves.high--;
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bc_.halves.high--;
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if(!bc_.halves.high) {
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if(!bc_.halves.high) {
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memptr_.full = pc_.full;
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advance_operation();
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advance_operation();
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}
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}
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break;
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break;
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@ -873,7 +872,7 @@ template < class T,
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break;
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break;
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case MicroOp::CalculateIndexAddress:
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case MicroOp::CalculateIndexAddress:
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memptr_.full = static_cast<uint16_t>(*static_cast<uint16_t *>(operation->source) + (int8_t)temp8_);
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memptr_.full = static_cast<uint16_t>(*static_cast<uint16_t *>(operation->source) + int8_t(temp8_));
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break;
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break;
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case MicroOp::SetAddrAMemptr:
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case MicroOp::SetAddrAMemptr:
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@ -371,7 +371,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
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DEC_INC_DEC_LD(bc_, bc_.halves.low),
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DEC_INC_DEC_LD(bc_, bc_.halves.low),
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/* 0x0f RRCA */ StdInstr({MicroOp::RRCA}),
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/* 0x0f RRCA */ StdInstr({MicroOp::RRCA}),
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/* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::Move16, &pc_.full, &memptr_.full}, {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
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/* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
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/* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)),
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/* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)),
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/* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)),
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/* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)),
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