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https://github.com/TomHarte/CLK.git
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Tackles outstanding GCC warnings.
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parent
4359fb1746
commit
8ace258fbc
@ -156,6 +156,8 @@ class ClockStorage {
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phase_ = Phase::Command;
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phase_ = Phase::Command;
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return DidComplete;
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return DidComplete;
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}
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}
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return NoResult;
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}
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}
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@ -763,10 +763,10 @@ Machine *Machine::Oric(const Analyser::Static::Target *target_hint, const ROMMac
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#define DiskInterfaceSwitch(processor) \
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#define DiskInterfaceSwitch(processor) \
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switch(oric_target->disk_interface) { \
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switch(oric_target->disk_interface) { \
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default: return new ConcreteMachine<DiskInterface::None, processor>(*oric_target, rom_fetcher); \
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default: return new ConcreteMachine<DiskInterface::None, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Microdisc: return new ConcreteMachine<DiskInterface::Microdisc, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Microdisc: return new ConcreteMachine<DiskInterface::Microdisc, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Pravetz: return new ConcreteMachine<DiskInterface::Pravetz, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Pravetz: return new ConcreteMachine<DiskInterface::Pravetz, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Jasmin: return new ConcreteMachine<DiskInterface::Jasmin, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::Jasmin: return new ConcreteMachine<DiskInterface::Jasmin, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::BD500: return new ConcreteMachine<DiskInterface::BD500, processor>(*oric_target, rom_fetcher); \
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case DiskInterface::BD500: return new ConcreteMachine<DiskInterface::BD500, processor>(*oric_target, rom_fetcher); \
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}
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}
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@ -777,6 +777,7 @@ Machine *Machine::Oric(const Analyser::Static::Target *target_hint, const ROMMac
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#undef DiskInterfaceSwitch
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#undef DiskInterfaceSwitch
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return nullptr;
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}
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}
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Machine::~Machine() {}
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Machine::~Machine() {}
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@ -276,7 +276,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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case OperationConstructAbsoluteXRead:
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case OperationConstructAbsoluteXRead:
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case OperationConstructAbsoluteX:
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case OperationConstructAbsoluteX:
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data_address_ = instruction_buffer_.value + registers_.x.full + registers_.data_bank;
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data_address_ = instruction_buffer_.value + registers_.x.full + registers_.data_bank;
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incorrect_data_address_ = (data_address_ & 0xff) | (instruction_buffer_.value & 0xff00) + registers_.data_bank;
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incorrect_data_address_ = ((data_address_ & 0x00ff) | (instruction_buffer_.value & 0xff00)) + registers_.data_bank;
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// If the incorrect address isn't actually incorrect, skip its usage.
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// If the incorrect address isn't actually incorrect, skip its usage.
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if(operation == OperationConstructAbsoluteXRead && data_address_ == incorrect_data_address_) {
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if(operation == OperationConstructAbsoluteXRead && data_address_ == incorrect_data_address_) {
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@ -323,10 +323,10 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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continue;
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continue;
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case OperationConstructDirectIndexedIndirect:
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case OperationConstructDirectIndexedIndirect:
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data_address_ = registers_.data_bank + (
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data_address_ = registers_.data_bank + ((
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((registers_.direct + registers_.x.full + instruction_buffer_.value) & registers_.e_masks[1]) +
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((registers_.direct + registers_.x.full + instruction_buffer_.value) & registers_.e_masks[1]) +
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(registers_.direct & registers_.e_masks[0])
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(registers_.direct & registers_.e_masks[0])
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) & 0xffff;
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) & 0xffff);
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data_address_increment_mask_ = 0x00'ff'ff;
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data_address_increment_mask_ = 0x00'ff'ff;
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if(!(registers_.direct&0xff)) {
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if(!(registers_.direct&0xff)) {
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