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Use the outer switch for addressing mode dispatch, saving a lot of syntax.

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This commit is contained in:
Thomas Harte 2022-06-13 08:57:49 -04:00
parent f316cbcf94
commit 8ada73b283
2 changed files with 94 additions and 167 deletions
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2
InstructionSets/M68k/Instruction.hpp
View File

@ -250,6 +250,8 @@ enum class AddressingMode: uint8_t {
/// .q; value is embedded in the opcode. /// .q; value is embedded in the opcode.
Quick = 0b01'110, Quick = 0b01'110,
}; };
/// Guaranteed to be 1+[largest value used by AddressingMode].
static constexpr int AddressingModeCount = 0b10'110;
/*! /*!
A preinstruction is as much of an instruction as can be decoded with A preinstruction is as much of an instruction as can be decoded with

259
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -17,6 +17,9 @@
namespace CPU { namespace CPU {
namespace MC68000Mk2 { namespace MC68000Mk2 {
#define AddressingDispatch(x) \
x, x##__end = x + InstructionSet::M68k::AddressingModeCount
/// States for the state machine which are named by /// States for the state machine which are named by
/// me for their purpose rather than automatically by file position. /// me for their purpose rather than automatically by file position.
/// These are negative to avoid ambiguity with the other group. /// These are negative to avoid ambiguity with the other group.
@ -25,11 +28,6 @@ enum ExecutionState: int {
Decode, Decode,
WaitForDTACK, WaitForDTACK,
/// Perform the proper sequence to fetch a byte or word operand.
FetchOperand_bw,
/// Perform the proper sequence to fetch a long-word operand.
FetchOperand_l,
StoreOperand, StoreOperand,
StoreOperand_bw, StoreOperand_bw,
StoreOperand_l, StoreOperand_l,
@ -64,42 +62,26 @@ enum ExecutionState: int {
// Further consideration may be necessary. Especially once this is // Further consideration may be necessary. Especially once this is
// up on its feet and profiling becomes an option. // up on its feet and profiling becomes an option.
FetchAddressRegisterIndirect_bw, /// Perform the proper sequence to fetch a byte or word operand.
FetchAddressRegisterIndirectWithPostincrement_bw, AddressingDispatch(FetchOperand_bw),
FetchAddressRegisterIndirectWithPredecrement_bw, /// Perform the proper sequence to fetch a long-word operand.
FetchAddressRegisterIndirectWithDisplacement_bw, AddressingDispatch(FetchOperand_l),
FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw, /// Perform the sequence to calculate an effective address, but don't fetch from it.
FetchProgramCounterIndirectWithDisplacement_bw, /// There's a lack of uniformity in the bus programs used by the 68000 for relevant
FetchProgramCounterIndirectWithIndex8bitDisplacement_bw, /// instructions; this entry point uses:
FetchAbsoluteShort_bw, ///
FetchAbsoluteLong_bw, /// Dn - An -
FetchImmediateData_bw, /// (An)+ - -(An) -
/// (d16, An) np (d8, An, Xn) np n
FetchAddressRegisterIndirect_l, /// (d16, PC) np (d8, PC, Xn) np n
FetchAddressRegisterIndirectWithPostincrement_l, /// (xxx).w np (xxx).l np np
FetchAddressRegisterIndirectWithPredecrement_l, AddressingDispatch(CalcEffectiveAddress),
FetchAddressRegisterIndirectWithDisplacement_l, /// Similar to CalcEffectiveAddress, but varies slightly in the patterns:
FetchAddressRegisterIndirectWithIndex8bitDisplacement_l, ///
FetchProgramCounterIndirectWithDisplacement_l, /// -(An) n
FetchProgramCounterIndirectWithIndex8bitDisplacement_l, /// (d8, An, Xn) n np n
FetchAbsoluteShort_l, /// (d8, PC, Xn) n np n
FetchAbsoluteLong_l, CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec,
FetchImmediateData_l,
CalcEffectiveAddress, // -
CalcAddressRegisterIndirect, // -
CalcAddressRegisterIndirectWithPostincrement, // -
CalcAddressRegisterIndirectWithPredecrement, // -
CalcAddressRegisterIndirectWithDisplacement, // np
CalcAddressRegisterIndirectWithIndex8bitDisplacement, // np n
CalcProgramCounterIndirectWithDisplacement, // np
CalcProgramCounterIndirectWithIndex8bitDisplacement, // np n
CalcAbsoluteShort, // np
CalcAbsoluteLong, // np np
CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec, // As per CalcEffectiveAddress unless one of the
// 8-bit displacement modes is in use, in which case
// an extra idle bus state is prefixed.
// Various forms of perform; each of these will // Various forms of perform; each of these will
// perform the current instruction, then do the // perform the current instruction, then do the
@ -189,6 +171,8 @@ enum ExecutionState: int {
ProgramCounterIndirectWithIndex8bitDisplacement_n_np, ProgramCounterIndirectWithIndex8bitDisplacement_n_np,
}; };
#undef AddressingDispatch
// MARK: - The state machine. // MARK: - The state machine.
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform> template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
@ -215,7 +199,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
#define MoveToStateDynamic(x) { state_ = x; continue; } #define MoveToStateDynamic(x) { state_ = x; continue; }
// Sets the start position for state x. // Sets the start position for state x.
#define BeginState(x) case ExecutionState::x: [[maybe_unused]] x #define BeginState(x) case ExecutionState::x: [[maybe_unused]] x
// Sets the start position for the addressing mode y within state x,
// where x was declared as an AddressingDispatch.
#define BeginStateMode(x, y) case ExecutionState::x + int(InstructionSet::M68k::AddressingMode::y) + 1
// Moves dynamically to addressing mode y within state x, where x was declared
// as an AddressingDispatch.
#define MoveToAddressingMode(x, y) MoveToStateDynamic(ExecutionState::x + int(y) + 1)
// //
// So basic structure is, in general: // So basic structure is, in general:
@ -1069,87 +1061,16 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
if(!(operand_flags_ & (1 << next_operand_))) { if(!(operand_flags_ & (1 << next_operand_))) {
MoveToStateDynamic(perform_state_); MoveToStateDynamic(perform_state_);
} }
MoveToAddressingMode(FetchOperand_bw, instruction_.mode(next_operand_));
// Figure out how to fetch it.
switch(instruction_.mode(next_operand_)) {
case Mode::AddressRegisterDirect:
case Mode::DataRegisterDirect:
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
MoveToNextOperand(FetchOperand_bw);
case Mode::Quick:
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
MoveToNextOperand(FetchOperand_bw);
case Mode::AddressRegisterIndirect:
MoveToStateSpecific(FetchAddressRegisterIndirect_bw);
case Mode::AddressRegisterIndirectWithPostincrement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithPostincrement_bw);
case Mode::AddressRegisterIndirectWithPredecrement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithPredecrement_bw);
case Mode::AddressRegisterIndirectWithDisplacement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithDisplacement_bw);
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
case Mode::ProgramCounterIndirectWithDisplacement:
MoveToStateSpecific(FetchProgramCounterIndirectWithDisplacement_bw);
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
case Mode::AbsoluteShort:
MoveToStateSpecific(FetchAbsoluteShort_bw);
case Mode::AbsoluteLong:
MoveToStateSpecific(FetchAbsoluteLong_bw);
case Mode::ImmediateData:
MoveToStateSpecific(FetchImmediateData_bw);
// Should be impossible to reach.
default:
assert(false);
}
break;
// As above, but for .l. // As above, but for .l.
BeginState(FetchOperand_l): BeginState(FetchOperand_l):
if(!(operand_flags_ & (1 << next_operand_))) { if(!(operand_flags_ & (1 << next_operand_))) {
MoveToStateDynamic(perform_state_); MoveToStateDynamic(perform_state_);
} }
MoveToAddressingMode(FetchOperand_l, instruction_.mode(next_operand_));
switch(instruction_.mode(next_operand_)) {
case Mode::AddressRegisterDirect:
case Mode::DataRegisterDirect:
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
MoveToNextOperand(FetchOperand_l);
case Mode::Quick:
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
MoveToNextOperand(FetchOperand_l);
case Mode::AddressRegisterIndirect:
MoveToStateSpecific(FetchAddressRegisterIndirect_l);
case Mode::AddressRegisterIndirectWithPostincrement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithPostincrement_l);
case Mode::AddressRegisterIndirectWithPredecrement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithPredecrement_l);
case Mode::AddressRegisterIndirectWithDisplacement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithDisplacement_l);
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
case Mode::ProgramCounterIndirectWithDisplacement:
MoveToStateSpecific(FetchProgramCounterIndirectWithDisplacement_l);
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
case Mode::AbsoluteShort:
MoveToStateSpecific(FetchAbsoluteShort_l);
case Mode::AbsoluteLong:
MoveToStateSpecific(FetchAbsoluteLong_l);
case Mode::ImmediateData:
MoveToStateSpecific(FetchImmediateData_l);
// Should be impossible to reach.
default:
assert(false);
}
break;
BeginState(CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec): BeginState(CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec):
if( if(
@ -1164,43 +1085,45 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
[[fallthrough]]; [[fallthrough]];
BeginState(CalcEffectiveAddress): BeginState(CalcEffectiveAddress):
switch(instruction_.mode(next_operand_)) { MoveToAddressingMode(CalcEffectiveAddress, instruction_.mode(next_operand_));
default:
MoveToStateDynamic(post_ea_state_);
case Mode::AddressRegisterIndirect:
MoveToStateSpecific(CalcAddressRegisterIndirect);
case Mode::AddressRegisterIndirectWithPostincrement:
MoveToStateSpecific(CalcAddressRegisterIndirectWithPostincrement);
case Mode::AddressRegisterIndirectWithPredecrement:
MoveToStateSpecific(CalcAddressRegisterIndirectWithPredecrement);
case Mode::AddressRegisterIndirectWithDisplacement:
MoveToStateSpecific(CalcAddressRegisterIndirectWithDisplacement);
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(CalcAddressRegisterIndirectWithIndex8bitDisplacement);
case Mode::ProgramCounterIndirectWithDisplacement:
MoveToStateSpecific(CalcProgramCounterIndirectWithDisplacement);
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
MoveToStateSpecific(CalcProgramCounterIndirectWithIndex8bitDisplacement);
case Mode::AbsoluteShort:
MoveToStateSpecific(CalcAbsoluteShort);
case Mode::AbsoluteLong:
MoveToStateSpecific(CalcAbsoluteLong);
}
// MARK: - Fetch, addressing modes. // MARK: - Fetch, addressing modes.
//
// DataRegisterDirect, AddressRegisterDirect
//
BeginStateMode(FetchOperand_bw, AddressRegisterDirect):
BeginStateMode(FetchOperand_bw, DataRegisterDirect):
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
MoveToNextOperand(FetchOperand_bw);
BeginStateMode(FetchOperand_l, AddressRegisterDirect):
BeginStateMode(FetchOperand_l, DataRegisterDirect):
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
MoveToNextOperand(FetchOperand_l);
//
// Quick
//
BeginStateMode(FetchOperand_bw, Quick):
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
MoveToNextOperand(FetchOperand_bw);
BeginStateMode(FetchOperand_l, Quick):
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
MoveToNextOperand(FetchOperand_l);
// //
// AddressRegisterIndirect // AddressRegisterIndirect
// //
BeginState(FetchAddressRegisterIndirect_bw): BeginStateMode(FetchOperand_bw, AddressRegisterIndirect):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAddressRegisterIndirect_l): BeginStateMode(FetchOperand_l, AddressRegisterIndirect):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1210,7 +1133,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAddressRegisterIndirect): BeginStateMode(CalcEffectiveAddress, AddressRegisterIndirect):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1222,7 +1145,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AddressRegisterIndirectWithPostincrement // AddressRegisterIndirectWithPostincrement
// //
BeginState(FetchAddressRegisterIndirectWithPostincrement_bw): BeginStateMode(FetchOperand_bw, AddressRegisterIndirectWithPostincrement):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
registers_[8 + instruction_.reg(next_operand_)].l += registers_[8 + instruction_.reg(next_operand_)].l +=
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)]; address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
@ -1231,7 +1154,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAddressRegisterIndirectWithPostincrement_l): BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithPostincrement):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
registers_[8 + instruction_.reg(next_operand_)].l += 4; registers_[8 + instruction_.reg(next_operand_)].l += 4;
@ -1241,7 +1164,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAddressRegisterIndirectWithPostincrement): BeginStateMode(CalcEffectiveAddress, AddressRegisterIndirectWithPostincrement):
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
registers_[8 + instruction_.reg(next_operand_)].l += registers_[8 + instruction_.reg(next_operand_)].l +=
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)]; address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
@ -1250,7 +1173,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AddressRegisterIndirectWithPredecrement // AddressRegisterIndirectWithPredecrement
// //
BeginState(FetchAddressRegisterIndirectWithPredecrement_bw): BeginStateMode(FetchOperand_bw, AddressRegisterIndirectWithPredecrement):
registers_[8 + instruction_.reg(next_operand_)].l -= registers_[8 + instruction_.reg(next_operand_)].l -=
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)]; address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
@ -1260,7 +1183,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAddressRegisterIndirectWithPredecrement_l): BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithPredecrement):
registers_[8 + instruction_.reg(next_operand_)].l -= 4; registers_[8 + instruction_.reg(next_operand_)].l -= 4;
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1271,7 +1194,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAddressRegisterIndirectWithPredecrement): BeginStateMode(CalcEffectiveAddress, AddressRegisterIndirectWithPredecrement):
registers_[8 + instruction_.reg(next_operand_)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)]; registers_[8 + instruction_.reg(next_operand_)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l; effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1279,7 +1202,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AddressRegisterIndirectWithDisplacement // AddressRegisterIndirectWithDisplacement
// //
BeginState(FetchAddressRegisterIndirectWithDisplacement_bw): BeginStateMode(FetchOperand_bw, AddressRegisterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1289,7 +1212,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAddressRegisterIndirectWithDisplacement_l): BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1301,7 +1224,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAddressRegisterIndirectWithDisplacement): BeginStateMode(CalcEffectiveAddress, AddressRegisterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1319,7 +1242,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// ProgramCounterIndirectWithDisplacement // ProgramCounterIndirectWithDisplacement
// //
BeginState(FetchProgramCounterIndirectWithDisplacement_bw): BeginStateMode(FetchOperand_bw, ProgramCounterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1329,7 +1252,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchProgramCounterIndirectWithDisplacement_l): BeginStateMode(FetchOperand_l, ProgramCounterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1341,7 +1264,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcProgramCounterIndirectWithDisplacement): BeginStateMode(CalcEffectiveAddress, ProgramCounterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
uint32_t(int16_t(prefetch_.w)); uint32_t(int16_t(prefetch_.w));
@ -1366,7 +1289,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
uint32_t(int16_t(registers_[prefetch_.w >> 12].w))) + \ uint32_t(int16_t(registers_[prefetch_.w >> 12].w))) + \
uint32_t(int8_t(prefetch_.b)); uint32_t(int8_t(prefetch_.b));
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw): BeginStateMode(FetchOperand_bw, AddressRegisterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l); effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1375,7 +1298,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l): BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l); effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1386,7 +1309,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement): BeginStateMode(CalcEffectiveAddress, AddressRegisterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l); effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
Prefetch(); // np Prefetch(); // np
IdleBus(1); // n IdleBus(1); // n
@ -1407,7 +1330,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// ProgramCounterIndirectWithIndex8bitDisplacement // ProgramCounterIndirectWithIndex8bitDisplacement
// //
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw): BeginStateMode(FetchOperand_bw, ProgramCounterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2); effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1416,7 +1339,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l): BeginStateMode(FetchOperand_l, ProgramCounterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2); effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1427,7 +1350,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement): BeginStateMode(CalcEffectiveAddress, ProgramCounterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2); effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
Prefetch(); // np Prefetch(); // np
IdleBus(1); // n IdleBus(1); // n
@ -1450,7 +1373,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AbsoluteShort // AbsoluteShort
// //
BeginState(FetchAbsoluteShort_bw): BeginStateMode(FetchOperand_bw, AbsoluteShort):
effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w)); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1458,7 +1381,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAbsoluteShort_l): BeginStateMode(FetchOperand_l, AbsoluteShort):
effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w)); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
@ -1468,7 +1391,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAbsoluteShort): BeginStateMode(CalcEffectiveAddress, AbsoluteShort):
effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w)); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
Prefetch(); // np Prefetch(); // np
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1482,7 +1405,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AbsoluteLong // AbsoluteLong
// //
BeginState(FetchAbsoluteLong_bw): BeginStateMode(FetchOperand_bw, AbsoluteLong):
Prefetch(); // np Prefetch(); // np
effective_address_[next_operand_].l = prefetch_.l; effective_address_[next_operand_].l = prefetch_.l;
@ -1492,7 +1415,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAbsoluteLong_l): BeginStateMode(FetchOperand_l, AbsoluteLong):
Prefetch(); // np Prefetch(); // np
effective_address_[next_operand_].l = prefetch_.l; effective_address_[next_operand_].l = prefetch_.l;
@ -1504,7 +1427,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].low); // nr Access(operand_[next_operand_].low); // nr
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAbsoluteLong): BeginStateMode(CalcEffectiveAddress, AbsoluteLong):
Prefetch(); // np Prefetch(); // np
effective_address_[next_operand_].l = prefetch_.l; effective_address_[next_operand_].l = prefetch_.l;
Prefetch(); // np Prefetch(); // np
@ -1519,12 +1442,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// ImmediateData // ImmediateData
// //
BeginState(FetchImmediateData_bw): BeginStateMode(FetchOperand_bw, ImmediateData):
operand_[next_operand_].w = prefetch_.w; operand_[next_operand_].w = prefetch_.w;
Prefetch(); // np Prefetch(); // np
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchImmediateData_l): BeginStateMode(FetchOperand_l, ImmediateData):
Prefetch(); // np Prefetch(); // np
operand_[next_operand_].l = prefetch_.l; operand_[next_operand_].l = prefetch_.l;
Prefetch(); // np Prefetch(); // np
@ -2573,6 +2496,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
#undef Spend #undef Spend
#undef ConsiderExit #undef ConsiderExit
#undef ReloadInstructionAddress #undef ReloadInstructionAddress
#undef MoveToAddressingMode
#undef BeginStateMode
} }