From 8b3c0abe93de951c14a584c1ee4411eff96b7b00 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 12 Mar 2024 09:13:05 -0400 Subject: [PATCH] Take another swing at R15 as a destination. --- InstructionSets/ARM/Executor.hpp | 16 +++------------- Machines/Acorn/Archimedes/Archimedes.cpp | 2 +- 2 files changed, 4 insertions(+), 14 deletions(-) diff --git a/InstructionSets/ARM/Executor.hpp b/InstructionSets/ARM/Executor.hpp index afc5da310..b31176ce8 100644 --- a/InstructionSets/ARM/Executor.hpp +++ b/InstructionSets/ARM/Executor.hpp @@ -178,22 +178,12 @@ struct Executor { break; } - const bool writes_pc = !is_comparison(flags.operation()) && fields.destination() == 15; - if(writes_pc) { + if(!is_comparison(flags.operation()) && fields.destination() == 15) { registers_.set_pc(pc_proxy); } if constexpr (flags.set_condition_codes()) { - // "When Rd is a register other than R15, the condition code flags in the PSR may be - // updated from the ALU flags as described above. When Rd is R15 and the S flag in - // the instruction is set, the PSR is overwritten by the corresponding ALU result. - // - // ... if the instruction is of a type which does not normally produce a result - // (CMP, CMN, TST, TEQ) but Rd is R15 and the S bit is set, the result will be used in - // this case to update those PSR flags which are not protected by virtue of the - // processor mode." - - if(writes_pc) { - registers_.set_status(pc_proxy); + if(fields.destination() == 15) { + registers_.set_status(conditions); } else { // Set N and Z in a unified way. registers_.set_nz(conditions); diff --git a/Machines/Acorn/Archimedes/Archimedes.cpp b/Machines/Acorn/Archimedes/Archimedes.cpp index d2aa5716a..fbff0aafd 100644 --- a/Machines/Acorn/Archimedes/Archimedes.cpp +++ b/Machines/Acorn/Archimedes/Archimedes.cpp @@ -750,7 +750,7 @@ class ConcreteMachine: all.insert(instruction); - if(executor_.pc() == 0x03801a0c) { + if(executor_.pc() == 0x03801a14) { printf(""); } // log |= (executor_.pc() > 0x02000000 && executor_.pc() < 0x02000078);