From 8b50ab2593c1e24a897b5962a2af417ab8deef6f Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 10 Aug 2018 21:12:55 -0400 Subject: [PATCH] Corrects (zero) behaviour. --- Processors/6502/Implementation/6502Implementation.hpp | 3 +++ Processors/6502/Implementation/6502Storage.cpp | 8 ++++---- Processors/6502/Implementation/6502Storage.hpp | 1 + 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Processors/6502/Implementation/6502Implementation.hpp b/Processors/6502/Implementation/6502Implementation.hpp index 7dbe6d069..ca0a371c6 100644 --- a/Processors/6502/Implementation/6502Implementation.hpp +++ b/Processors/6502/Implementation/6502Implementation.hpp @@ -429,6 +429,9 @@ if(number_of_cycles <= Cycles(0)) break; operand_ += x_; read_mem(address_.bytes.low, operand_); break; + case CycleFetchAddressLowFromOperand: + read_mem(address_.bytes.low, operand_); + break; case CycleIncrementOperandFetchAddressHigh: operand_++; read_mem(address_.bytes.high, operand_); diff --git a/Processors/6502/Implementation/6502Storage.cpp b/Processors/6502/Implementation/6502Storage.cpp index 385ea326d..786394d45 100644 --- a/Processors/6502/Implementation/6502Storage.cpp +++ b/Processors/6502/Implementation/6502Storage.cpp @@ -22,14 +22,14 @@ using namespace CPU::MOS6502; #define Zero OperationLoadAddressZeroPage #define ZeroX CycleLoadAddessZeroX #define ZeroY CycleLoadAddessZeroY -#define ZeroIndirect OperationLoadAddressZeroPage, CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh +#define ZeroIndirect OperationLoadAddressZeroPage, CycleFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh #define IndexedIndirect CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh #define IndirectIndexedr CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLow, OperationCorrectAddressHigh #define IndirectIndexed CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLowRead, OperationCorrectAddressHigh #define Read(...) CycleFetchOperandFromAddress, __VA_ARGS__ #define Write(...) __VA_ARGS__, CycleWriteOperandToAddress -#define ReadModifyWrite(...) CycleFetchOperandFromAddress, CycleWriteOperandToAddress, __VA_ARGS__, CycleWriteOperandToAddress +#define ReadModifyWrite(...) CycleFetchOperandFromAddress, (personality == P6502) ? CycleWriteOperandToAddress : CycleFetchOperandFromAddress, __VA_ARGS__, CycleWriteOperandToAddress #define AbsoluteRead(op) Program(Absolute, Read(op)) #define AbsoluteXRead(op) Program(AbsoluteXr, Read(op)) @@ -282,9 +282,9 @@ ProcessorStorage::ProcessorStorage(Personality personality) { Install(0x32, ZeroIndirectRead(OperationAND)); Install(0x52, ZeroIndirectRead(OperationEOR)); Install(0x72, ZeroIndirectRead(OperationADC)); - Install(0x92, ZeroIndirectRead(OperationSTA)); + Install(0x92, ZeroIndirectWrite(OperationSTA)); Install(0xb2, ZeroIndirectRead(OperationLDA)); - Install(0xd2, ZeroIndirectWrite(OperationCMP)); + Install(0xd2, ZeroIndirectRead(OperationCMP)); Install(0xd2, ZeroIndirectRead(OperationSBC)); } #undef Install diff --git a/Processors/6502/Implementation/6502Storage.hpp b/Processors/6502/Implementation/6502Storage.hpp index ec48d8d36..50d24727b 100644 --- a/Processors/6502/Implementation/6502Storage.hpp +++ b/Processors/6502/Implementation/6502Storage.hpp @@ -45,6 +45,7 @@ class ProcessorStorage { OperationMoveToNextProgram, OperationIncrementPC, CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA, CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand, + CycleFetchAddressLowFromOperand, OperationIncrementOperand, OperationORA, OperationAND, OperationEOR, OperationINS, OperationADC, OperationSBC, OperationLDA, OperationLDX, OperationLDY, OperationLAX, OperationSTA,