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Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).

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This commit is contained in:
Thomas Harte 2017-05-29 17:13:24 -04:00
parent 0d067d2f01
commit 8bfaa487ce
2 changed files with 15 additions and 10 deletions
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9
OSBindings/Mac/Clock SignalTests/Bridges/TestMachineZ80.mm
View File

@ -89,7 +89,14 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
@implementation CSTestMachineZ80BusOperationCapture
- (NSString *)description {
return [NSString stringWithFormat:@"%c %04x %02x [%d]", (self.operation == CSTestMachineZ80BusOperationCaptureOperationRead) ? 'r' : 'w', self.address, self.value, self.timeStamp];
NSString *opName = @"";
switch(self.operation) {
case CSTestMachineZ80BusOperationCaptureOperationRead: opName = @"r"; break;
case CSTestMachineZ80BusOperationCaptureOperationWrite: opName = @"w"; break;
case CSTestMachineZ80BusOperationCaptureOperationPortRead: opName = @"i"; break;
case CSTestMachineZ80BusOperationCaptureOperationPortWrite: opName = @"o"; break;
}
return [NSString stringWithFormat:@"%@ %04x %02x [%d]", opName, self.address, self.value, self.timeStamp];
}
@end

16
Processors/Z80/Z80.hpp
View File

@ -118,7 +118,7 @@ struct MicroOp {
LDI, LDIR, LDD, LDDR,
CPI, CPIR, CPD, CPDR,
INI, INIR, IND, INDR,
OUTI, OUTIR, OUTD, OUTDR,
OUTI, OUTD, OUT_R,
RLA, RLCA, RRA, RRCA,
RLC, RRC, RL, RR,
@ -393,22 +393,22 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
/* 0xa0 LDI */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDI}),
/* 0xa1 CPI */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPI}),
/* 0xa2 INI */ Program(WAIT(1), IN(bc_, temp8_), STOREL(temp8_, hl_), {MicroOp::INI}),
/* 0xa3 OTI */ Program(WAIT(1), FETCHL(temp8_, hl_), OUT(bc_, temp8_), {MicroOp::OUTI}),
/* 0xa3 OTI */ Program(WAIT(1), FETCHL(temp8_, hl_), {MicroOp::OUTI}, OUT(bc_, temp8_)),
NOP, NOP, NOP, NOP,
/* 0xa8 LDD */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDD}),
/* 0xa9 CPD */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPD}),
/* 0xaa IND */ Program(WAIT(1), IN(bc_, temp8_), STOREL(temp8_, hl_), {MicroOp::IND}),
/* 0xab OTD */ Program(WAIT(1), FETCHL(temp8_, hl_), OUT(bc_, temp8_), {MicroOp::OUTD}),
/* 0xab OTD */ Program(WAIT(1), FETCHL(temp8_, hl_), {MicroOp::OUTD}, OUT(bc_, temp8_)),
NOP, NOP, NOP, NOP,
/* 0xb0 LDIR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDIR}, WAIT(5)),
/* 0xb1 CPIR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPIR}, WAIT(5)),
/* 0xb2 INIR */ Program(WAIT(1), IN(bc_, temp8_), STOREL(temp8_, hl_), {MicroOp::INIR}, WAIT(5)),
/* 0xb3 OTIR */ Program(WAIT(1), FETCHL(temp8_, hl_), OUT(bc_, temp8_), {MicroOp::OUTIR}, WAIT(5)),
/* 0xb3 OTIR */ Program(WAIT(1), FETCHL(temp8_, hl_), {MicroOp::OUTI}, OUT(bc_, temp8_), {MicroOp::OUT_R}, WAIT(5)),
NOP, NOP, NOP, NOP,
/* 0xb8 LDDR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDDR}, WAIT(5)),
/* 0xb9 CPDR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPDR}, WAIT(5)),
/* 0xba INDR */ Program(WAIT(1), IN(bc_, temp8_), STOREL(temp8_, hl_), {MicroOp::INDR}, WAIT(5)),
/* 0xbb OTDR */ Program(WAIT(1), FETCHL(temp8_, hl_), OUT(bc_, temp8_), {MicroOp::OUTDR}, WAIT(5)),
/* 0xbb OTDR */ Program(WAIT(1), FETCHL(temp8_, hl_), {MicroOp::OUTD}, OUT(bc_, temp8_), {MicroOp::OUT_R}, WAIT(5)),
NOP, NOP, NOP, NOP,
NOP_ROW(), /* 0xc0 */
NOP_ROW(), /* 0xd0 */
@ -1187,11 +1187,9 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
summation = (summation&7) ^ bc_.bytes.high; \
set_parity(summation);
case MicroOp::OUTDR:
case MicroOp::OUTIR: {
OUTxR_STEP(MicroOp::OUTIR);
case MicroOp::OUT_R:
REPEAT(bc_.bytes.high);
} break;
break;
case MicroOp::OUTD:
case MicroOp::OUTI: {