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https://github.com/TomHarte/CLK.git
synced 2025-08-08 14:25:05 +00:00
Adds a delay on vsync visibility (i.e. as to generating an interrupt).
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@@ -99,13 +99,13 @@ const int vsync_x_position = CYCLE(56); // Horizontal cycle on which vertical s
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const int hsync_start = CYCLE(48); // Cycles before end of line when hsync starts.
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const int hsync_start = CYCLE(48); // Cycles before end of line when hsync starts.
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const int hsync_end = CYCLE(8); // Cycles before end of line when hsync ends.
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const int hsync_end = CYCLE(8); // Cycles before end of line when hsync ends.
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const int hsync_delay_period = hsync_end; // Signal hsync at the end of the line.
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const int hsync_delay_period = hsync_end; // Signal hsync at the end of the line.
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const int vsync_delay_period = hsync_delay_period; // Signal vsync with the same delay as hsync.
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// "VSYNC starts 104 cycles after the start of the previous line's HSYNC, so that's 4 cycles before DE would be activated. ";
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// "VSYNC starts 104 cycles after the start of the previous line's HSYNC, so that's 4 cycles before DE would be activated. ";
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// that's an inconsistent statement since it would imply VSYNC at +54, which is 2 cycles before DE in 60Hz mode and 6 before
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// that's an inconsistent statement since it would imply VSYNC at +54, which is 2 cycles before DE in 60Hz mode and 6 before
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// in 50Hz mode. I've gone with 56, to be four cycles ahead of DE in 50Hz mode.
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// in 50Hz mode. I've gone with 56, to be four cycles ahead of DE in 50Hz mode.
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//
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// TODO: some sort of latency on vsync and hsync visibility, I would imagine?
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}
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}
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@@ -183,6 +183,7 @@ void Video::advance(HalfCycles duration) {
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const int run_length = std::min(integer_duration, next_event - x_);
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const int run_length = std::min(integer_duration, next_event - x_);
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const bool display_enable = vertical_.enable && horizontal_.enable;
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const bool display_enable = vertical_.enable && horizontal_.enable;
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const bool hsync = horizontal_.sync;
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const bool hsync = horizontal_.sync;
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const bool vsync = vertical_.sync;
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// Ensure proper fetching irrespective of the output.
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// Ensure proper fetching irrespective of the output.
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if(load_) {
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if(load_) {
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@@ -339,6 +340,11 @@ void Video::advance(HalfCycles duration) {
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// Schedule change in outwardly-visible hsync line.
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// Schedule change in outwardly-visible hsync line.
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add_event(hsync_delay_period - integer_duration, horizontal_.sync ? Event::Type::SetHsync : Event::Type::ResetHsync);
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add_event(hsync_delay_period - integer_duration, horizontal_.sync ? Event::Type::SetHsync : Event::Type::ResetHsync);
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}
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}
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if(vertical_.sync != vsync) {
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// Schedule change in outwardly-visible hsync line.
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add_event(vsync_delay_period - integer_duration, horizontal_.sync ? Event::Type::SetVsync : Event::Type::ResetVsync);
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}
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}
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}
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}
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}
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@@ -364,7 +370,7 @@ bool Video::hsync() {
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}
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}
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bool Video::vsync() {
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bool Video::vsync() {
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return vertical_.sync;
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return public_state_.vsync;
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}
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}
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bool Video::display_enabled() {
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bool Video::display_enabled() {
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@@ -228,6 +228,7 @@ class Video {
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struct PublicState {
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struct PublicState {
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bool display_enable = false;
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bool display_enable = false;
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bool hsync = false;
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bool hsync = false;
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bool vsync = false;
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} public_state_;
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} public_state_;
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struct Event {
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struct Event {
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@@ -235,6 +236,7 @@ class Video {
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enum class Type {
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enum class Type {
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SetDisplayEnable, ResetDisplayEnable,
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SetDisplayEnable, ResetDisplayEnable,
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SetHsync, ResetHsync,
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SetHsync, ResetHsync,
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SetVsync, ResetVsync,
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} type;
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} type;
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Event(Type type, int delay) : delay(delay), type(type) {}
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Event(Type type, int delay) : delay(delay), type(type) {}
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@@ -250,6 +252,8 @@ class Video {
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case Type::ResetDisplayEnable: state.display_enable = false; break;
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case Type::ResetDisplayEnable: state.display_enable = false; break;
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case Type::SetHsync: state.hsync = true; break;
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case Type::SetHsync: state.hsync = true; break;
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case Type::ResetHsync: state.hsync = false; break;
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case Type::ResetHsync: state.hsync = false; break;
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case Type::SetVsync: state.vsync = true; break;
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case Type::ResetVsync: state.vsync = false; break;
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}
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}
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}
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}
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};
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};
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