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https://github.com/TomHarte/CLK.git
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Imports third-party tests for ABCD, and thereby fixes ABCD.
This commit is contained in:
Thomas Harte
parent
8182b0363f
commit
8dace34e63
@ -11,6 +11,7 @@
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#include <array>
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#include <cassert>
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#define LOG_TRACE
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#include "68000.hpp"
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/*!
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@ -66,17 +67,18 @@ class RAM68000: public CPU::MC68000::BusHandler {
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = ram_[word_address];
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printf("r %04x from %08x \n", cycle.value->full, *cycle.address);
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = ram_[word_address] >> cycle.byte_shift();
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break;
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case Microcycle::SelectWord:
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printf("w %08x of %04x\n", *cycle.address, cycle.value->full);
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ram_[word_address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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ram_[word_address] = (cycle.value->full & cycle.byte_mask()) | (ram_[word_address] & (0xffff ^ cycle.byte_mask()));
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ram_[word_address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(ram_[word_address] & cycle.untouched_byte_mask())
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);
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break;
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}
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}
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@ -208,7 +210,7 @@ class CPU::MC68000::ProcessorStorageTests {
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_machine.reset();
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}
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- (void)testABCD {
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- (void)testABCDLong {
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for(int d = 0; d < 100; ++d) {
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_machine.reset(new RAM68000());
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_machine->set_program({
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@ -515,4 +517,134 @@ class CPU::MC68000::ProcessorStorageTests {
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// XCTAssert(!falseInvalids.count, "%@ opcodes should be valid but aren't: %@", @(falseInvalids.count), falseInvalids.hexDump);
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}
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// MARK: - Tests below this line were ported from those of the Portable 68k emulator;
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// that emulator does not include a licence. It reports that all tests were verified
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// against an Amiga.
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- (void)testABCD {
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_machine->set_program({
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0xc302, // ABCD D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x1234567a;
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state.data[2] = 0xf745ff78;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Carry);
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XCTAssertEqual(state.data[1], 0x12345658);
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XCTAssertEqual(state.data[2], 0xf745ff78);
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}
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- (void)testABCDZero {
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_machine->set_program({
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0xc302, // ABCD D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x12345600;
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state.data[2] = 0x12345600;
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state.status = CPU::MC68000::Flag::Zero;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Zero);
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XCTAssertEqual(state.data[1], 0x12345600);
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XCTAssertEqual(state.data[2], 0x12345600);
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}
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- (void)testABCDNegative {
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_machine->set_program({
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0xc302, // ABCD D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x12345645;
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state.data[2] = 0x12345654;
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state.status = CPU::MC68000::Flag::Zero;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Negative);
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XCTAssertEqual(state.data[1], 0x12345699);
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XCTAssertEqual(state.data[2], 0x12345654);
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}
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- (void)testABCDWithX {
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_machine->set_program({
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0xc302, // ABCD D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x12345645;
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state.data[2] = 0x12345654;
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state.status = CPU::MC68000::Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Carry);
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XCTAssertEqual(state.data[1], 0x12345600);
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XCTAssertEqual(state.data[2], 0x12345654);
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}
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- (void)testABCDOverflow {
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_machine->set_program({
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0xc302, // ABCD D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x1234563e;
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state.data[2] = 0x1234563e;
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state.status = CPU::MC68000::Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Overflow);
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XCTAssertEqual(state.data[1], 0x12345683);
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XCTAssertEqual(state.data[2], 0x1234563e);
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}
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- (void)testABCDPredecDifferent {
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_machine->set_program({
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0xc30a, // ABCD -(A2), -(A1)
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});
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*_machine->ram_at(0x3000) = 0xa200;
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*_machine->ram_at(0x4000) = 0x1900;
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auto state = _machine->get_processor_state();
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state.address[1] = 0x3001;
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state.address[2] = 0x4001;
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state.status = CPU::MC68000::Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Carry);
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XCTAssert(state.status & CPU::MC68000::Flag::Extend);
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XCTAssertEqual(state.address[1], 0x3000);
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XCTAssertEqual(state.address[2], 0x4000);
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x2200);
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XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);
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}
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- (void)testABCDPredecSame {
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_machine->set_program({
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0xc309, // ABCD -(A1), -(A1)
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});
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*_machine->ram_at(0x3000) = 0x19a2;
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auto state = _machine->get_processor_state();
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state.address[1] = 0x3002;
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state.status = CPU::MC68000::Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssert(state.status & CPU::MC68000::Flag::Carry);
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XCTAssert(state.status & CPU::MC68000::Flag::Extend);
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XCTAssertEqual(state.address[1], 0x3000);
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x22a2);
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}
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@end
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@ -53,7 +53,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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const HalfCycles remaining_duration = duration + half_cycles_left_to_run_;
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#ifdef LOG_TRACE
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static bool should_log = false;
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static bool should_log = true;
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#endif
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// This loop counts upwards rather than downwards because it simplifies calculation of
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@ -289,10 +289,10 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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}
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#ifdef LOG_TRACE
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const uint32_t fetched_pc = (program_counter_.full - 4)&0xffffff;
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// const uint32_t fetched_pc = (program_counter_.full - 4)&0xffffff;
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should_log |= fetched_pc == 0x401142;
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should_log &= fetched_pc != 0x4011AA;
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// should_log |= fetched_pc == 0x401142;
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// should_log &= fetched_pc != 0x4011AA;
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// should_log = (fetched_pc >= 0x408D66) && (fetched_pc <= 0x408D84);
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#endif
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@ -808,7 +808,7 @@ struct ProcessorStorageConstructor {
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// Temporary storage for the Program fields.
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ProcessorBase::Program program;
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// if(instruction == 0xc302) {
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// if(instruction == 0xc30a) {
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// printf("");
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// }
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@ -1831,26 +1831,15 @@ struct ProcessorStorageConstructor {
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// Decodes the format used by ABCD and SBCD.
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case Decoder::ABCD_SBCD: {
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if(instruction & 8) {
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program.source = &storage_.source_bus_data_[0];
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program.destination = &storage_.destination_bus_data_[0];
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program.source_address = &storage_.address_[ea_register];
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program.destination_address = &storage_.address_[data_register];
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program.set_source(storage_, Ind, ea_register);
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program.set_destination(storage_, Ind, data_register);
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const int source_dec = dec(ea_register);
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const int destination_dec = dec(data_register);
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int first_action = source_dec | MicroOp::SourceMask | MicroOp::DestinationMask;
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if(source_dec != destination_dec) {
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first_action = source_dec | MicroOp::SourceMask;
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op(destination_dec | MicroOp::DestinationMask);
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}
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op( first_action,
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seq("n nr nrd np nw", { a(ea_register), a(data_register), a(data_register) }, false));
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op(Action::PerformOperation);
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op(MicroOp::SourceMask | dec(ea_register), seq("n nr", { a(ea_register) }, false ));
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op(MicroOp::DestinationMask | dec(data_register), seq("nrd np", { a(data_register) }, false ));
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op(Action::PerformOperation, seq("nw", { a(data_register) }, false));
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} else {
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program.source = &storage_.data_[ea_register];
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program.destination = &storage_.data_[data_register];
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program.set_source(storage_, Dn, ea_register);
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program.set_destination(storage_, Dn, data_register);
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op(Action::PerformOperation, seq("np n"));
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}
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