Attempts proactively to ensure proper RTI behaviour on the 65816.

Processors/6502Esque/6502Esque.hpp

@@ -64,13 +64,17 @@ enum Flag: uint8_t {
 	isReadOperation macro to make a binary choice between reading and writing.
 */
 enum BusOperation {
-	Read, ReadOpcode, Write, Ready, None
+	Read,
+	ReadOpcode,
+	Write,
+	Ready,
+	None
 };
 
 /*!
-	Evaluates to `true` if the operation is a read; `false` if it is a write.
+	Evaluates to `true` if the operation is a read; `false` if it is a write or ready.
 */
-#define isReadOperation(v)	(v == CPU::MOS6502Esque::BusOperation::Read || v == CPU::MOS6502Esque::BusOperation::ReadOpcode)
+#define isReadOperation(v)	(v < CPU::MOS6502Esque::BusOperation::Write)
 
 /*!
 	A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,

Processors/65816/Implementation/65816Implementation.hpp

@@ -153,6 +153,12 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
 				--s_.full;
 			break;
 
+			case CyclePullIfNotEmulation:
+				if(emulation_flag_) {
+					continue;
+				}
+			[[fallthrough]];
+
 			case CyclePull:
 				++s_.full;
 				stack_access(data_buffer_.next_input(), MOS6502Esque::Read);

Processors/65816/Implementation/65816Storage.cpp

@@ -652,18 +652,16 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
 	}
 
 	// 22g. Stack; s, RTI.
-	static void stack_rti(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
-		target(CycleFetchPCThrowaway);	// IO
-		target(CycleFetchPCThrowaway);	// IO
+	static void stack_rti(AccessType, bool, const std::function<void(MicroOp)> &target) {
+		target(CycleFetchPCThrowaway);		// IO
+		target(CycleFetchPCThrowaway);		// IO
 
-		target(CyclePull);				// P
-		target(CyclePull);				// New PCL
-		target(CyclePull);				// New PCH
-		if(!is8bit) target(CyclePull);	// PBR
-		// TODO: 8bit check here doesn't actually work, it needs to be an is-emulation-mode check.
-		// New operation needed, I think.
+		target(CyclePull);					// P
+		target(CyclePull);					// New PCL
+		target(CyclePull);					// New PCH
+		target(CyclePullIfNotEmulation);	// PBR
 
-		target(OperationPerform);		// [RTI] — to unpack the fields above.
+		target(OperationPerform);			// [RTI] — to unpack the fields above.
 	}
 
 	// 22h. Stack; s, RTS.

Processors/65816/Implementation/65816Storage.hpp

@@ -44,6 +44,8 @@ enum MicroOp: uint8_t {
 	CycleAccessStack,
 	/// Pulls a single byte to the data buffer from the stack.
 	CyclePull,
+	/// Performs as CyclePull if the 65816 is not in emulation mode; otherwise skips itself.
+	CyclePullIfNotEmulation,
 
 	/// Sets the data address by copying the final two bytes of the instruction buffer and
 	/// using the data register as a high byte.