diff --git a/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift b/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift
index 17dfda582..d2d4f5107 100644
--- a/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift	
+++ b/OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift	
@@ -90,6 +90,10 @@ class KlausDormannTests: XCTestCase {
 				case 0x1983: return "STZ didn't store zero"
 
 				case 0x1b03: return "BIT didn't set flags correctly"
+				case 0x1c6c: return "BIT immediate didn't set flags correctly"
+
+				case 0x1d88: return "TRB set Z flag incorrectly"
+				case 0x1e7c: return "RMB set flags incorrectly"
 
 				case 0: return "Didn't find tests"
 				default: return "Unknown error at \(String(format:"%04x", address))"
diff --git a/Processors/6502/Implementation/6502Implementation.hpp b/Processors/6502/Implementation/6502Implementation.hpp
index d9888d29b..b8a52f2e6 100644
--- a/Processors/6502/Implementation/6502Implementation.hpp
+++ b/Processors/6502/Implementation/6502Implementation.hpp
@@ -108,6 +108,9 @@ if(number_of_cycles <= Cycles(0)) break;
 					break;
 
 					case OperationDecodeOperation:
+						if(operation_ == 0x89) {
+							printf("");
+						}
 						scheduled_program_counter_ = operations_[operation_];
 					continue;
 
@@ -231,13 +234,24 @@ if(number_of_cycles <= Cycles(0)) break;
 						carry_flag_ = ((~temp16) >> 8)&1;
 					} continue;
 
-// MARK: - BIT
+// MARK: - BIT, TSB, TRB
 
 					case OperationBIT:
 						zero_result_ = operand_ & a_;
 						negative_result_ = operand_;
 						overflow_flag_ = operand_&Flag::Overflow;
 					continue;
+					case OperationBITNoNV:
+						zero_result_ = operand_ & a_;
+					continue;
+					case OperationTRB:
+						zero_result_ = operand_ & a_;
+						operand_ &= ~a_;
+					continue;
+					case OperationTSB:
+						zero_result_ = operand_ & a_;
+						operand_ |= a_;
+					continue;
 
 // MARK: - ADC/SBC (and INS)
 
diff --git a/Processors/6502/Implementation/6502Storage.cpp b/Processors/6502/Implementation/6502Storage.cpp
index 49292b030..7ef8ae728 100644
--- a/Processors/6502/Implementation/6502Storage.cpp
+++ b/Processors/6502/Implementation/6502Storage.cpp
@@ -292,6 +292,17 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
 		Install(0x9e, AbsoluteXWrite(OperationSTZ));
 		Install(0x64, ZeroWrite(OperationSTZ));
 		Install(0x74, ZeroXWrite(OperationSTZ));
+
+		// Add the extra BITs.
+		Install(0x34, ZeroXRead(OperationBIT));
+		Install(0x3c, AbsoluteXRead(OperationBIT));
+		Install(0x89, Immediate(OperationBITNoNV));
+
+		// Add TRB and TSB.
+		Install(0x04, ZeroReadModifyWrite(OperationTSB));
+		Install(0x0c, AbsoluteReadModifyWrite(OperationTSB));
+		Install(0x14, ZeroReadModifyWrite(OperationTRB));
+		Install(0x1c, AbsoluteReadModifyWrite(OperationTRB));
 	}
 #undef Install
 }
diff --git a/Processors/6502/Implementation/6502Storage.hpp b/Processors/6502/Implementation/6502Storage.hpp
index cde267786..8e41934ea 100644
--- a/Processors/6502/Implementation/6502Storage.hpp
+++ b/Processors/6502/Implementation/6502Storage.hpp
@@ -52,11 +52,13 @@ class ProcessorStorage {
 			OperationSTX,								OperationSTY,						OperationSTZ,
 			OperationSAX,								OperationSHA,
 			OperationSHX,								OperationSHY,						OperationSHS,							OperationCMP,
-			OperationCPX,								OperationCPY,						OperationBIT,							OperationASL,
+			OperationCPX,								OperationCPY,						OperationBIT,							OperationBITNoNV,
+			OperationASL,
 			OperationASO,								OperationROL,						OperationRLA,							OperationLSR,
 			OperationLSE,								OperationASR,						OperationROR,							OperationRRA,
 			OperationCLC,								OperationCLI,						OperationCLV,							OperationCLD,
 			OperationSEC,								OperationSEI,						OperationSED,
+			OperationTRB,								OperationTSB,
 
 			OperationINC,								OperationDEC,						OperationINX,							OperationDEX,
 			OperationINY,								OperationDEY,						OperationINA,							OperationDEA,