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Adjusted HALT to issue never-ending M1 fetches on the next instruction.

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Thomas Harte 2017-05-29 12:20:33 -04:00
parent ed7b07c8b1
commit 91dc0d5f4a
1 changed files with 1 additions and 2 deletions
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3
Processors/Z80/Z80.hpp
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@ -707,7 +707,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
case MicroOp::DecodeOperation: case MicroOp::DecodeOperation:
if(current_instruction_page_->increments_r) r_ = (r_ & 0x80) | ((r_ + 1) & 0x7f); if(current_instruction_page_->increments_r) r_ = (r_ & 0x80) | ((r_ + 1) & 0x7f);
pc_.full++; pc_.full++;
decode_operation(operation_); decode_operation(is_halted_ ? 0x00 : operation_);
break; break;
case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break; case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break;
@ -1385,7 +1385,6 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
case MicroOp::HALT: case MicroOp::HALT:
is_halted_ = true; is_halted_ = true;
pc_.full --;
break; break;
#pragma mark - Internal bookkeeping #pragma mark - Internal bookkeeping