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Attempts properly to honour the bus-op and microcycle contract.
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@ -9,12 +9,49 @@
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template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::run_for(HalfCycles duration) {
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template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::run_for(HalfCycles duration) {
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// TODO: obey the 'cycles' count.
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// TODO: obey the 'cycles' count.
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while(true) {
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while(true) {
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// Check whether the current list of bus steps is exhausted; if so then
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// seek out another one from the current program (if any), and if there
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/*
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// are no more to do, revert to scheduling something else (after checking
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PERFORM THE CURRENT BUS STEP'S MICROCYCLE.
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// for interrupts).
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*/
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if(active_step_->action == BusStep::Action::ScheduleNextProgram) {
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// Check for DTack if this isn't being treated implicitly.
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if(active_micro_op_) {
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if(!dtack_is_implicit) {
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if(active_step_->microcycle.data_select_active() && !dtack_) {
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// TODO: perform wait state.
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continue;
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}
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}
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// TODO: synchronous bus.
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// Perform the microcycle.
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bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
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/*
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PERFORM THE BUS STEP'S ACTION.
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*/
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// Consider advancing a micro-operation.
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if(active_step_->is_terminal()) {
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// If there are any more micro-operations available, just move onwards.
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if(active_micro_op_ && !active_micro_op_->is_terminal()) {
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++active_micro_op_;
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} else {
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// Either the micro-operations for this instruction have been exhausted, or
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// no instruction was ongoing. Either way, do a standard instruction operation.
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// TODO: unless an interrupt is pending, or the trap flag is set.
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const uint16_t next_instruction = prefetch_queue_[0].full;
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if(!instructions[next_instruction].micro_operations) {
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std::cerr << "68000 Abilities exhausted; should schedule an instruction or something?" << std::endl;
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return;
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}
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active_program_ = &instructions[next_instruction];
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active_micro_op_ = active_program_->micro_operations;
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}
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// There is now a micro operation; cue up the first step and perform the predecessor action.
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active_step_ = active_micro_op_->bus_program;
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switch(active_micro_op_->action) {
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switch(active_micro_op_->action) {
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case MicroOp::Action::None: break;
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case MicroOp::Action::None: break;
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@ -98,42 +135,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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active_program_->destination->full -= 4;
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active_program_->destination->full -= 4;
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break;
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break;
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}
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}
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}
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if(active_micro_op_) {
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} else {
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++active_micro_op_;
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active_step_ = active_micro_op_->bus_program;
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}
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if(!active_step_ || !active_micro_op_) {
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const uint16_t next_instruction = prefetch_queue_[0].full;
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if(!instructions[next_instruction].micro_operations) {
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std::cerr << "68000 Abilities exhausted; should schedule an instruction or something?" << std::endl;
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return;
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}
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active_program_ = &instructions[next_instruction];
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active_micro_op_ = active_program_->micro_operations;
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active_step_ = active_micro_op_->bus_program;
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}
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}
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// The bus step list is not exhausted, so perform the microcycle.
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// Check for DTack if this isn't being treated implicitly.
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if(!dtack_is_implicit) {
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if(active_step_->microcycle.data_select_active() && !dtack_) {
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// TODO: perform wait state.
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continue;
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}
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}
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// TODO: synchronous bus.
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// Perform the microcycle.
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bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
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// Perform the post-hoc action.
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switch(active_step_->action) {
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switch(active_step_->action) {
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default:
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default:
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std::cerr << "Unimplemented 68000 bus step action: " << int(active_step_->action) << std::endl;
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std::cerr << "Unimplemented 68000 bus step action: " << int(active_step_->action) << std::endl;
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@ -150,7 +153,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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break;
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break;
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}
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}
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// Move to the next program step.
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// Move to the next bus step.
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++active_step_;
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++ active_step_;
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}
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}
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}
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}
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}
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@ -260,9 +260,7 @@ struct ProcessorStorageConstructor {
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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for(size_t instruction = 0; instruction < 65536; ++instruction) {
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for(const auto &mapping: mappings) {
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for(const auto &mapping: mappings) {
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if((instruction & mapping.mask) == mapping.value) {
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if((instruction & mapping.mask) == mapping.value) {
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// Install the operation and make a note of where micro-ops begin.
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const auto micro_op_start = storage_.all_micro_ops_.size();
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storage_.instructions[instruction].operation = mapping.operation;
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micro_op_pointers[instruction] = storage_.all_micro_ops_.size();
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switch(mapping.decoder) {
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switch(mapping.decoder) {
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case Decoder::Decimal: {
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case Decoder::Decimal: {
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@ -288,14 +286,15 @@ struct ProcessorStorageConstructor {
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}
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}
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} break;
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} break;
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case Decoder::RegOpModeReg: {
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} break;
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default:
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default:
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std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
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std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
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break;
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continue;
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}
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}
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// Install the operation and make a note of where micro-ops begin.
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storage_.instructions[instruction].operation = mapping.operation;
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micro_op_pointers[instruction] = micro_op_start;
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// Don't search further through the list of possibilities.
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// Don't search further through the list of possibilities.
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break;
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break;
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}
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}
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@ -309,7 +308,9 @@ struct ProcessorStorageConstructor {
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auto operation = storage_.instructions[instruction].micro_operations;
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auto operation = storage_.instructions[instruction].micro_operations;
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while(!operation->is_terminal()) {
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while(!operation->is_terminal()) {
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operation->bus_program = storage_.all_bus_steps_.data() + (operation->bus_program - &arbitrary_base);
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const auto offset = size_t(operation->bus_program - &arbitrary_base);
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assert(offset >= 0 && offset < storage_.all_bus_steps_.size());
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operation->bus_program = &storage_.all_bus_steps_[offset];
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++operation;
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++operation;
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}
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}
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}
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}
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@ -45,6 +45,7 @@ class ProcessorStorage {
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/*!
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/*!
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Bus steps are sequences of things to communicate to the bus.
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Bus steps are sequences of things to communicate to the bus.
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Standard behaviour is: (i) perform microcycle; (ii) perform action.
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*/
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*/
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struct BusStep {
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struct BusStep {
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Microcycle microcycle;
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Microcycle microcycle;
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@ -69,17 +70,26 @@ class ProcessorStorage {
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} action = Action::None;
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} action = Action::None;
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bool operator ==(const BusStep &rhs) const {
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inline bool operator ==(const BusStep &rhs) const {
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if(action != rhs.action) return false;
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if(action != rhs.action) return false;
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return microcycle == rhs.microcycle;
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return microcycle == rhs.microcycle;
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}
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}
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inline bool is_terminal() const {
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return action == Action::ScheduleNextProgram;
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}
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};
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};
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/*!
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/*!
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A micro-op is: (i) an action to take; and (ii) a sequence of bus operations
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A micro-op is: (i) an action to take; and (ii) a sequence of bus operations
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to perform after taking the action.
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to perform after taking the action.
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A nullptr bus_program terminates a sequence of micro operations.
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NOTE: this therefore has the opposite order of behaviour compared to a BusStep,
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the action occurs BEFORE the bus operations, not after.
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A nullptr bus_program terminates a sequence of micro operations; the is_terminal
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test should be used to query for that. The action on the final operation will
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be performed.
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*/
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*/
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struct MicroOp {
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struct MicroOp {
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enum class Action {
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enum class Action {
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