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Attempt a more compact retelling.
This commit is contained in:
Thomas Harte
parent
b965f2053a
commit
94e5436f6e
@ -143,140 +143,95 @@ constexpr Operation Predecoder<model>::operation(OpT op) {
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template <Model model>
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template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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constexpr auto Dn = Mask< AddressingMode::DataRegisterDirect >::value;
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constexpr auto An = Mask< AddressingMode::AddressRegisterDirect >::value;
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constexpr auto Ind = Mask< AddressingMode::AddressRegisterIndirect >::value;
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constexpr auto PostInc = Mask< AddressingMode::AddressRegisterIndirectWithPostincrement >::value;
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constexpr auto PreDec = Mask< AddressingMode::AddressRegisterIndirectWithPredecrement >::value;
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constexpr auto d16An = Mask< AddressingMode::AddressRegisterIndirectWithDisplacement >::value;
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constexpr auto d8AnXn = Mask< AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement >::value;
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constexpr auto XXXw = Mask< AddressingMode::AbsoluteShort >::value;
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constexpr auto XXXl = Mask< AddressingMode::AbsoluteLong >::value;
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constexpr auto d16PC = Mask< AddressingMode::ProgramCounterIndirectWithDisplacement >::value;
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constexpr auto d8PCXn = Mask< AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement >::value;
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constexpr auto Imm = Mask< AddressingMode::ImmediateData >::value;
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constexpr auto Quick = Mask< AddressingMode::Quick >::value;
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// A few recurring combinations; terminology is directly from
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// the Programmers' Reference Manual.
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//
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// All modes: the complete set.
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// All modes: the complete set (other than Quick).
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//
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// (and the complete set without AddressRegisterDirect, for byte operations).
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static constexpr uint32_t AllModes = Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterDirect,
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AddressingMode::AddressRegisterIndirect,
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AddressingMode::AddressRegisterIndirectWithPostincrement,
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AddressingMode::AddressRegisterIndirectWithPredecrement,
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AddressingMode::AddressRegisterIndirectWithDisplacement,
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AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement,
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AddressingMode::AbsoluteShort,
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AddressingMode::AbsoluteLong,
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AddressingMode::ImmediateData,
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AddressingMode::ProgramCounterIndirectWithDisplacement,
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AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement
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>::value;
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static constexpr uint32_t AllModes_b = Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterIndirect,
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AddressingMode::AddressRegisterIndirectWithPostincrement,
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AddressingMode::AddressRegisterIndirectWithPredecrement,
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AddressingMode::AddressRegisterIndirectWithDisplacement,
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AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement,
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AddressingMode::AbsoluteShort,
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AddressingMode::AbsoluteLong,
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AddressingMode::ImmediateData,
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AddressingMode::ProgramCounterIndirectWithDisplacement,
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AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement
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>::value;
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static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn | Imm;
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static constexpr auto AllModes_b = AllModes & ~An;
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//
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// Alterable addressing modes (with and without AddressRegisterDirect).
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//
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// Dn, An, (An), (An)+, -(An), (d16, An), (d8, An, Xn), (xxx).W, (xxx).L
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// (and sans An for _b)
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static constexpr uint32_t AlterableAddressingModes = Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterDirect,
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AddressingMode::AddressRegisterIndirect,
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AddressingMode::AddressRegisterIndirectWithPostincrement,
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AddressingMode::AddressRegisterIndirectWithPredecrement,
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AddressingMode::AddressRegisterIndirectWithDisplacement,
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AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement,
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AddressingMode::AbsoluteShort,
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AddressingMode::AbsoluteLong
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>::value;
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static constexpr uint32_t AlterableAddressingModes_b = Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterIndirect,
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AddressingMode::AddressRegisterIndirectWithPostincrement,
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AddressingMode::AddressRegisterIndirectWithPredecrement,
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AddressingMode::AddressRegisterIndirectWithDisplacement,
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AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement,
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AddressingMode::AbsoluteShort,
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AddressingMode::AbsoluteLong
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>::value;
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static constexpr auto AlterableAddressingModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl;
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static constexpr auto AlterableAddressingModes_b = AlterableAddressingModes & ~An;
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switch(op) {
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default: return NoOperandMask::value;
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case OpT(Operation::ABCD):
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case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl):
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return ~TwoOperandMask<Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterIndirectWithPredecrement
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>::value, Mask<
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AddressingMode::DataRegisterDirect,
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AddressingMode::AddressRegisterIndirectWithPredecrement
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>::value>::value;
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return ~TwoOperandMask<
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Dn | PreDec,
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Dn | PreDec
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>::value;
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case ADDtoRb:
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return ~TwoOperandMask<
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AllModes_b
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, Mask<
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AddressingMode::DataRegisterDirect
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>::value>::value;
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AllModes_b,
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Dn
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>::value;
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case ADDtoRw: case ADDtoRl:
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return ~TwoOperandMask<
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AllModes
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, Mask<
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AddressingMode::DataRegisterDirect
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>::value>::value;
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AllModes,
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Dn
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>::value;
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case ADDtoMb: case ADDtoMw: case ADDtoMl:
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return ~TwoOperandMask<Mask<
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AddressingMode::DataRegisterDirect
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>::value, Mask<
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// TODO: I strongly suspect this should be AlterableAddressingModes regardless
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// of the documentation. Verify.
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AddressingMode::AddressRegisterIndirect,
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AddressingMode::AddressRegisterIndirectWithPostincrement,
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AddressingMode::AddressRegisterIndirectWithPredecrement,
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AddressingMode::AddressRegisterIndirectWithDisplacement,
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AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement,
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AddressingMode::AbsoluteShort,
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AddressingMode::AbsoluteLong
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>::value>::value;
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return ~TwoOperandMask<
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Dn,
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Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
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return ~TwoOperandMask<
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AllModes
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, Mask<
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AddressingMode::AddressRegisterDirect
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>::value>::value;
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AllModes,
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An
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>::value;
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case ADDIb: case ADDIl: case ADDIw:
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return ~TwoOperandMask<Mask<
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AddressingMode::ImmediateData
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>::value,
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return ~TwoOperandMask<
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Imm,
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AlterableAddressingModes_b
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>::value;
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case ADDQb:
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return ~TwoOperandMask<Mask<
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AddressingMode::Quick
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>::value,
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return ~TwoOperandMask<
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Quick,
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AlterableAddressingModes_b
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>::value;
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case ADDQw: case ADDQl:
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return ~TwoOperandMask<Mask<
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AddressingMode::Quick
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>::value,
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return ~TwoOperandMask<
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Quick,
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AlterableAddressingModes
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>::value;
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case OpT(Operation::NBCD):
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return ~OneOperandMask<AlterableAddressingModes_b>::value;
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return ~OneOperandMask<
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AlterableAddressingModes_b
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>::value;
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}
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}
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@ -363,11 +318,9 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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}
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// ADD, SUB, MOVE, MOVEA
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// case ADDQb: case ADDQw: case ADDQl:
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case SUBQb: case SUBQw: case SUBQl:
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case OpT(Operation::MOVEb): case OpT(Operation::MOVEw): case OpT(Operation::MOVEl):
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case OpT(Operation::MOVEAw): case OpT(Operation::MOVEAl):
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case OpT(Operation::ANDb): case OpT(Operation::ANDw): case OpT(Operation::ANDl):
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case OpT(Operation::EORb): case OpT(Operation::EORw): case OpT(Operation::EORl):
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case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
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// TODO: I'm going to need get-size-by-operation elsewhere; use that here when implemented.
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@ -724,31 +677,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// b0–b2 and b3–b5: an effective address;
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// b6–b8: an opmode, i.e. source + direction.
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//
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case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
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case OpT(Operation::ANDb): case OpT(Operation::ANDw): case OpT(Operation::ANDl):
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case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
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const auto ea_combined_mode = combined_mode(ea_mode, ea_register);
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// TODO: make this decision outside of this function.
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if(opmode & 4) {
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// Dn, <ea>
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return validated<op, validate>(
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Preinstruction(operation,
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AddressingMode::DataRegisterDirect, data_register,
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ea_combined_mode, ea_register));
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} else {
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// <ea>, Dn
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return validated<op, validate>(
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Preinstruction(operation,
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register));
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}
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return Preinstruction();
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}
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case ADDtoRb: case ADDtoRw: case ADDtoRl:
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