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Switched to a more authentic interfacing to the AY.
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@ -108,3 +108,41 @@ uint8_t AY38910::get_port_output(bool port_b)
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{
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return _registers[port_b ? 15 : 14];
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}
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void AY38910::set_data_input(uint8_t r)
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{
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_data_input = r;
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}
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uint8_t AY38910::get_data_output()
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{
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return _data_output;
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}
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void AY38910::set_control_lines(ControlLines control_lines)
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{
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ControlState new_state;
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switch((int)control_lines)
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{
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default: new_state = Inactive; break;
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case (int)(BCDIR | BC2 | BC1):
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case BCDIR:
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case BC1: new_state = LatchAddress; break;
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case (int)(BC2 | BC1): new_state = Read; break;
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case (int)(BCDIR | BC2): new_state = Write; break;
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}
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if(new_state != _control_state)
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{
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_control_state = new_state;
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switch(new_state)
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{
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default: break;
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case LatchAddress: select_register(_data_input); break;
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case Write: set_register_value(_data_input); break;
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case Read: _data_output = get_register_value(); break;
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}
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}
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}
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@ -21,9 +21,14 @@ class AY38910: public ::Outputs::Filter<AY38910> {
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void get_samples(unsigned int number_of_samples, int16_t *target);
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void skip_samples(unsigned int number_of_samples);
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void select_register(uint8_t r);
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void set_register_value(uint8_t value);
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uint8_t get_register_value();
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enum ControlLines {
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BC1 = (1 << 0),
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BC2 = (1 << 1),
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BCDIR = (1 << 2)
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};
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void set_data_input(uint8_t r);
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uint8_t get_data_output();
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void set_control_lines(ControlLines control_lines);
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uint8_t get_port_output(bool port_b);
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@ -39,6 +44,19 @@ class AY38910: public ::Outputs::Filter<AY38910> {
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int _envelope_divider;
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int _evelope_volume;
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int _channel_ouput[3];
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enum ControlState {
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Inactive,
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LatchAddress,
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Read,
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Write
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} _control_state;
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void select_register(uint8_t r);
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void set_register_value(uint8_t value);
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uint8_t get_register_value();
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uint8_t _data_input, _data_output;
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};
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};
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@ -119,8 +119,7 @@ class Machine:
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}
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else
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{
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_port_a_output = value;
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update_ay();
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ay8910->set_data_input(value);
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}
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}
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@ -132,7 +131,7 @@ class Machine:
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}
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else
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{
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return _port_a_input;
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return ay8910->get_data_output();
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}
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}
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@ -152,18 +151,8 @@ class Machine:
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void update_ay()
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{
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ay8910->run_for_cycles(_half_cycles_since_ay_update >> 1);
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_half_cycles_since_ay_update &= 1;
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if(_ay_bdir)
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{
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if(_ay_bc1) ay8910->select_register(_port_a_output);
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else ay8910->set_register_value(_port_a_output);
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}
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else
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{
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if(_ay_bc1) _port_a_input = ay8910->get_register_value();
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}
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ay8910->set_control_lines( (GI::AY38910::ControlLines)((_ay_bdir ? GI::AY38910::BCDIR : 0) | (_ay_bc1 ? GI::AY38910::BC1 : 0) | GI::AY38910::BC2));
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}
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uint8_t _port_a_output, _port_a_input;
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bool _ay_bdir, _ay_bc1;
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unsigned int _half_cycles_since_ay_update;
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};
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