diff --git a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
index 924734280..8608babd3 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
@@ -155,42 +155,8 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
 #endif
 
 	// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
-	_fileSet = [NSSet setWithArray:@[
-		@"abcd_sbcd.json",
-		@"add_sub.json",
-		@"addi_subi_cmpi.json",
-		@"addq_subq.json",
-		@"addx_subx.json",
-		@"bcc.json",
-		@"btst_bchg_bclr_bset.json",
-		@"chk.json",
-		@"cmp.json",
-		@"dbcc_scc.json",
-		@"divu_divs.json",
-		@"eor_and_or.json",
-		@"eori_andi_ori.json",
-		@"exg.json",
-		@"ext.json",
-		@"jmp_jsr.json",
-		@"lea.json",
-//		@"link_unlk.json",
-		@"lslr_aslr_roxlr_rolr.json",
-		@"move_tofrom_srccr.json",
-		@"move.json",
-		@"movem.json",
-		@"movep.json",
-		@"moveq.json",
-		@"mulu_muls.json",
-		@"nbcd_pea.json",
-		@"neg_not.json",
-		@"negx_clr.json",
-		@"rtr.json",
-		@"rts.json",
-		@"swap.json",
-		@"tas.json",
-		@"tst.json",
-	]];
-//	_testSet = [NSSet setWithArray:@[@"ASL/R e0d0"]];
+//	_fileSet = [NSSet setWithArray:@[@"abcd_sbcd.json"]];
+//	_testSet = [NSSet setWithArray:@[@"UNLK 0007"]];
 }
 
 - (void)testAll {
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index cacb11a2f..0f5e71a31 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -169,6 +169,8 @@ enum ExecutionState: int {
 	RTR,
 	RTE,
 	RTS,
+	LINK,
+	UNLINK,
 };
 
 // MARK: - The state machine.
@@ -764,9 +766,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				ShiftGroup(b, Perform_idle_dyamic_Dn)
 				ShiftGroup(w, Perform_idle_dyamic_Dn)
 				ShiftGroup(l, Perform_idle_dyamic_Dn)
-
 #undef ShiftGroup
 
+				StdCASE(LINKw, MoveToStateSpecific(LINK));
+				StdCASE(UNLINK, MoveToStateSpecific(UNLINK));
+
 				default:
 					assert(false);
 			}
@@ -1592,6 +1596,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 	Access(x.low);								\
 	registers_[15].l -= 2;
 
+#define Pop(x)													\
+	SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);	\
+	SetDataAddress(registers_[15].l);							\
+	Access(x.high);												\
+	registers_[15].l += 2;										\
+	Access(x.low);												\
+	registers_[15].l += 2;
+
 		//
 		// BSR
 		//
@@ -2103,6 +2115,23 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Prefetch();
 		MoveToStateSpecific(Decode);
 
+		//
+		// LINK and UNLINK
+		//
+		BeginState(LINK):
+			Prefetch();
+			Push(registers_[8 + instruction_.reg(0)]);
+			registers_[8 + instruction_.reg(0)].l = registers_[15].l + uint32_t(int16_t(prefetch_.high.w));
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(UNLINK):
+			registers_[15] = registers_[8 + instruction_.reg(0)];
+			Pop(temporary_address_);
+			registers_[8 + instruction_.reg(0)] = temporary_address_;
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
 		//
 		// Various states TODO.
 		//
@@ -2118,6 +2147,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			assert(false);
 	}}
 
+#undef Pop
 #undef Push
 #undef PerformDynamic
 #undef PerformSpecific