6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-18 08:31:04 +00:00
Code Issues Projects Releases Wiki Activity

Fix UNLINK A7.

Browse Source
This commit is contained in:
Thomas Harte 2022-05-23 10:27:44 -04:00
parent 26bf66e3f8
commit 98325325b1
2 changed files with 33 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
View File

@ -155,42 +155,8 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
#endif #endif
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below. // To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
_fileSet = [NSSet setWithArray:@[ // _fileSet = [NSSet setWithArray:@[@"abcd_sbcd.json"]];
@"abcd_sbcd.json", // _testSet = [NSSet setWithArray:@[@"UNLK 0007"]];
@"add_sub.json",
@"addi_subi_cmpi.json",
@"addq_subq.json",
@"addx_subx.json",
@"bcc.json",
@"btst_bchg_bclr_bset.json",
@"chk.json",
@"cmp.json",
@"dbcc_scc.json",
@"divu_divs.json",
@"eor_and_or.json",
@"eori_andi_ori.json",
@"exg.json",
@"ext.json",
@"jmp_jsr.json",
@"lea.json",
// @"link_unlk.json",
@"lslr_aslr_roxlr_rolr.json",
@"move_tofrom_srccr.json",
@"move.json",
@"movem.json",
@"movep.json",
@"moveq.json",
@"mulu_muls.json",
@"nbcd_pea.json",
@"neg_not.json",
@"negx_clr.json",
@"rtr.json",
@"rts.json",
@"swap.json",
@"tas.json",
@"tst.json",
]];
// _testSet = [NSSet setWithArray:@[@"ASL/R e0d0"]];
} }
- (void)testAll { - (void)testAll {

32
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -169,6 +169,8 @@ enum ExecutionState: int {
RTR, RTR,
RTE, RTE,
RTS, RTS,
LINK,
UNLINK,
}; };
// MARK: - The state machine. // MARK: - The state machine.
@ -764,9 +766,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
ShiftGroup(b, Perform_idle_dyamic_Dn) ShiftGroup(b, Perform_idle_dyamic_Dn)
ShiftGroup(w, Perform_idle_dyamic_Dn) ShiftGroup(w, Perform_idle_dyamic_Dn)
ShiftGroup(l, Perform_idle_dyamic_Dn) ShiftGroup(l, Perform_idle_dyamic_Dn)
#undef ShiftGroup #undef ShiftGroup
StdCASE(LINKw, MoveToStateSpecific(LINK));
StdCASE(UNLINK, MoveToStateSpecific(UNLINK));
default: default:
assert(false); assert(false);
} }
@ -1592,6 +1596,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(x.low); \ Access(x.low); \
registers_[15].l -= 2; registers_[15].l -= 2;
#define Pop(x) \
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); \
SetDataAddress(registers_[15].l); \
Access(x.high); \
registers_[15].l += 2; \
Access(x.low); \
registers_[15].l += 2;
// //
// BSR // BSR
// //
@ -2103,6 +2115,23 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); Prefetch();
MoveToStateSpecific(Decode); MoveToStateSpecific(Decode);
//
// LINK and UNLINK
//
BeginState(LINK):
Prefetch();
Push(registers_[8 + instruction_.reg(0)]);
registers_[8 + instruction_.reg(0)].l = registers_[15].l + uint32_t(int16_t(prefetch_.high.w));
Prefetch();
MoveToStateSpecific(Decode);
BeginState(UNLINK):
registers_[15] = registers_[8 + instruction_.reg(0)];
Pop(temporary_address_);
registers_[8 + instruction_.reg(0)] = temporary_address_;
Prefetch();
MoveToStateSpecific(Decode);
// //
// Various states TODO. // Various states TODO.
// //
@ -2118,6 +2147,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
assert(false); assert(false);
}} }}
#undef Pop
#undef Push #undef Push
#undef PerformDynamic #undef PerformDynamic
#undef PerformSpecific #undef PerformSpecific