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Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
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@ -159,10 +159,6 @@ class FUSETests: XCTestCase {
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let name = itemDictionary["name"] as! String
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let name = itemDictionary["name"] as! String
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// if name != "cb06" {
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// continue
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// }
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let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
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let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
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let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
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let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
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@ -1026,7 +1026,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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case MicroOp::BIT: {
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case MicroOp::BIT: {
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uint8_t result = *(uint8_t *)operation->source & (1 << ((operation_ >> 3)&7));
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uint8_t result = *(uint8_t *)operation->source & (1 << ((operation_ >> 3)&7));
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sign_result_ = zero_result_ = bit3_result_ = bit5_result_ = result;
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sign_result_ = zero_result_ = result;
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bit3_result_ = bit5_result_ = *(uint8_t *)operation->source; // This is a divergence between FUSE and The Undocumented Z80 Documented.
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half_carry_flag_ = Flag::HalfCarry;
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half_carry_flag_ = Flag::HalfCarry;
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subtract_flag_ = 0;
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subtract_flag_ = 0;
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parity_overflow_flag_ = result ? 0 : Flag::Parity;
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parity_overflow_flag_ = result ? 0 : Flag::Parity;
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