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https://github.com/TomHarte/CLK.git
synced 2025-04-05 04:37:41 +00:00
Add a mere calculate effective address pathway.
Plus a lot of waffle to try to justify the further code duplication.
This commit is contained in:
Thomas Harte
parent
c7c12f9638
commit
9d79e64f5c
@ -38,6 +38,30 @@ enum ExecutionState: int {
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BusOrAddressErrorException,
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// Specific addressing mode fetches.
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//
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// Additional context here is that I'm very much on the fence but
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// for now am telling myself:
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//
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// (1) the overwhelming majority of instructions that need an
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// effective address calculation use it for an operand read
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// immediately afterwards, so keeping those things bound
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// avoids a large number of conditional branches; and
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// (2) making a decision between byte/word and long-word once at
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// the outset also saves a conditional for any two-operand
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// instructions (which is also the majority); but
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// (3) some instructions do just need the address calculation —
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// LEA and PEA are obvious examples, but are not the
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// exhaustive list — so a third route just to do the
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// calculation is necessary.
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//
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// My internal dialogue then argues that each of these is actually
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// a small amount of code, so the need manually to duplicate (per
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// the control-flow constraints of using a switch as a coroutine)
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// isn't too ugly. Possibly even less ugly than pulling things out
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// with a macro, especially for debugging.
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//
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// Further consideration may be necessary. Especially once this is
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// up on its feet and profiling becomes an option.
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FetchAddressRegisterIndirect_bw,
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FetchAddressRegisterIndirectWithPostincrement_bw,
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@ -61,6 +85,17 @@ enum ExecutionState: int {
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FetchAbsoluteLong_l,
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FetchImmediateData_l,
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CalcEffectiveAddress,
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CalcAddressRegisterIndirect,
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CalcAddressRegisterIndirectWithPostincrement,
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CalcAddressRegisterIndirectWithPredecrement,
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CalcAddressRegisterIndirectWithDisplacement,
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CalcAddressRegisterIndirectWithIndex8bitDisplacement,
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CalcProgramCounterIndirectWithDisplacement,
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CalcProgramCounterIndirectWithIndex8bitDisplacement,
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CalcAbsoluteShort,
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CalcAbsoluteLong,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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@ -719,6 +754,32 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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break;
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BeginState(CalcEffectiveAddress):
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switch(instruction_.mode(next_operand_)) {
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default:
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state_ = post_ea_state_;
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break;
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case Mode::AddressRegisterIndirect:
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MoveToState(CalcAddressRegisterIndirect);
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case Mode::AddressRegisterIndirectWithPostincrement:
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MoveToState(CalcAddressRegisterIndirectWithPostincrement);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToState(CalcAddressRegisterIndirectWithPredecrement);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(CalcAddressRegisterIndirectWithDisplacement);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(CalcAddressRegisterIndirectWithIndex8bitDisplacement);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(CalcProgramCounterIndirectWithDisplacement);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(CalcProgramCounterIndirectWithIndex8bitDisplacement);
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case Mode::AbsoluteShort:
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MoveToState(CalcAbsoluteShort);
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case Mode::AbsoluteLong:
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MoveToState(CalcAbsoluteLong);
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}
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// MARK: - Fetch, addressing modes.
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//
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@ -741,13 +802,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAddressRegisterIndirect):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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state_ = post_ea_state_;
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break;
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//
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// AddressRegisterIndirectWithPostincrement
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//
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BeginState(FetchAddressRegisterIndirectWithPostincrement_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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registers_[8 + instruction_.reg(next_operand_)].l +=
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byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].low); // nr
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@ -763,12 +829,19 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAddressRegisterIndirectWithPostincrement):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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registers_[8 + instruction_.reg(next_operand_)].l +=
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address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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state_ = post_ea_state_;
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break;
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//
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// AddressRegisterIndirectWithPredecrement
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//
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BeginState(FetchAddressRegisterIndirectWithPredecrement_bw):
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registers_[8 + instruction_.reg(next_operand_)].l -=
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byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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@ -787,6 +860,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAddressRegisterIndirectWithPredecrement):
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registers_[8 + instruction_.reg(next_operand_)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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state_ = post_ea_state_;
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break;
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//
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// AddressRegisterIndirectWithDisplacement
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//
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@ -812,6 +891,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAddressRegisterIndirectWithDisplacement):
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effective_address_[next_operand_] =
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registers_[8 + instruction_.reg(next_operand_)].l +
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int16_t(prefetch_.w);
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Prefetch(); // np
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state_ = post_ea_state_;
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break;
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//
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// ProgramCounterIndirectWithDisplacement
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//
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@ -837,6 +925,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcProgramCounterIndirectWithDisplacement):
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effective_address_[next_operand_] =
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program_counter_.l - 2 +
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int16_t(prefetch_.w);
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Prefetch(); // np
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state_ = post_ea_state_;
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break;
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//
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// AddressRegisterIndirectWithIndex8bitDisplacement
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//
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#define d8Xn(base) \
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base + \
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((prefetch_.w & 0x800) ? \
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@ -844,9 +944,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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int16_t(registers_[prefetch_.w >> 12].w)) + \
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int8_t(prefetch_.b);
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//
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// AddressRegisterIndirectWithIndex8bitDisplacement
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//
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BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
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effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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SetDataAddress(effective_address_[next_operand_]);
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@ -867,6 +964,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement):
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effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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IdleBus(1); // n
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state_ = post_ea_state_;
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break;
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//
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// ProgramCounterIndirectWithIndex8bitDisplacement
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//
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@ -880,7 +983,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l):
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effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);;
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effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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@ -890,6 +993,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement):
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effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);
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IdleBus(1); // n
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state_ = post_ea_state_;
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break;
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#undef d8Xn
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//
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@ -913,6 +1022,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAbsoluteShort):
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effective_address_[next_operand_] = int16_t(prefetch_.w);
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Prefetch(); // np
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state_ = post_ea_state_;
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break;
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//
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// AbsoluteLong
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//
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@ -938,6 +1053,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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BeginState(CalcAbsoluteLong):
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Prefetch(); // np
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effective_address_[next_operand_] = prefetch_.l;
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Prefetch(); // np
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state_ = post_ea_state_;
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break;
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//
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// ImmediateData
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//
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@ -1079,11 +1201,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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SetupDataAccess(Microcycle::Read, select_flag_);
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SetDataAddress(registers_[8 + instruction_.reg(0)].l);
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registers_[8 + instruction_.reg(0)].l -= byte_word_increments[int(instruction_.operand_size())][instruction_.reg(0)];
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registers_[8 + instruction_.reg(0)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(0)];
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Access(operand_[0].low); // nr
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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registers_[8 + instruction_.reg(1)].l -= byte_word_increments[int(instruction_.operand_size())][instruction_.reg(1)];
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registers_[8 + instruction_.reg(1)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
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Access(operand_[1].low); // nr
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Prefetch(); // np
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@ -68,6 +68,10 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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/// into the proper exception.
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int post_dtack_state_ = 0;
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/// If using CalcEffectiveAddress, this is the state to adopt after the
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/// effective address for next_operand_ has been calculated.
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int post_ea_state_ = 0;
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/// The perform state for this operation.
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int perform_state_ = 0;
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@ -95,47 +99,56 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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/// determine total operation cost.
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bool did_bit_op_high_ = false;
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// Flow controller... all TODO.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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static constexpr uint32_t byte_word_increments[2][8] = {
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// A lookup table that aids with effective address calculation in
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// predecrement and postincrement modes; index as [size][register]
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// and note that [0][7] is 2 rather than 1.
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static constexpr uint32_t address_increments[3][8] = {
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{ 1, 1, 1, 1, 1, 1, 1, 2, },
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{ 2, 2, 2, 2, 2, 2, 2, 2, }
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{ 2, 2, 2, 2, 2, 2, 2, 2, },
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{ 4, 4, 4, 4, 4, 4, 4, 4, },
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};
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static_assert(int(InstructionSet::M68k::DataSize::Byte) == 0);
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static_assert(int(InstructionSet::M68k::DataSize::Word) == 1);
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static_assert(int(InstructionSet::M68k::DataSize::LongWord) == 2);
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/// Used by some dedicated read-modify-write perform patterns to
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/// determine the size of the bus operation.
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Microcycle::OperationT select_flag_ = 0;
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template <typename IntT> void did_mulu(IntT) {}
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template <typename IntT> void did_muls(IntT) {}
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// Flow controller... many TODO.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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template <typename IntT> void did_mulu(IntT) {} //
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template <typename IntT> void did_muls(IntT) {} //
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inline void did_chk(bool, bool);
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inline void did_scc(bool);
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inline void did_shift(int) {}
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template <bool did_overflow> void did_divu(uint32_t, uint32_t) {}
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template <bool did_overflow> void did_divs(int32_t, int32_t) {}
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inline void did_shift(int) {} //
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template <bool did_overflow> void did_divu(uint32_t, uint32_t) {} //
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template <bool did_overflow> void did_divs(int32_t, int32_t) {} //
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inline void did_bit_op(int);
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inline void did_update_status();
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template <typename IntT> void complete_bcc(bool, IntT);
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inline void complete_dbcc(bool, bool, int16_t);
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inline void bsr(uint32_t);
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inline void jsr(uint32_t) {}
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inline void jmp(uint32_t) {}
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inline void rtr() {}
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inline void rte() {}
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inline void rts() {}
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inline void stop() {}
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inline void reset() {}
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inline void link(Preinstruction, uint32_t) {}
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inline void unlink(uint32_t &) {}
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inline void pea(uint32_t) {}
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inline void move_to_usp(uint32_t) {}
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inline void move_from_usp(uint32_t &) {}
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inline void tas(Preinstruction, uint32_t) {}
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inline void jsr(uint32_t) {} //
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inline void jmp(uint32_t) {} //
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inline void rtr() {} //
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inline void rte() {} //
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inline void rts() {} //
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inline void stop() {} //
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inline void reset() {} //
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inline void link(Preinstruction, uint32_t) {} //
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inline void unlink(uint32_t &) {} //
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inline void pea(uint32_t) {} //
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inline void move_to_usp(uint32_t) {} //
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inline void move_from_usp(uint32_t &) {} //
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inline void tas(Preinstruction, uint32_t) {} //
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template <bool use_current_instruction_pc = true> void raise_exception(int) {}
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// These aren't implemented because the specific details of the implementation
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// mean that the performer call-out isn't necessary.
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template <typename IntT> void movep(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toM(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toR(Preinstruction, uint32_t, uint32_t) {}
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template <bool use_current_instruction_pc = true> void raise_exception(int) {}
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// Some microcycles that will be modified as required and used in the main loop;
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// the semantics of a switch statement make in-place declarations awkward and
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