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Implements the fixed part of register shifts.
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@ -921,7 +921,13 @@ struct ProcessorStorageConstructor {
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case Decoder::ASLRLSLRROLRROXLRr: {
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storage_.instructions[instruction].set_destination(storage_, 0, ea_register);
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// All decoding occurs at runtime.
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// All further decoding occurs at runtime; that's also when the proper number of
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// no-op cycles will be scheduled.
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if(((instruction >> 6) & 3) == 2) {
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op(Action::None, seq("np nn"));
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} else {
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op(Action::None, seq("np n"));
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}
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op(Action::PerformOperation);
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} break;
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