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Ensures that MOVE.b #, (xxx).l writes only a byte.

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Also rearranges some of the temporary logging functionality.
This commit is contained in:
Thomas Harte 2019-04-23 19:01:58 -04:00
parent 7c132a3ed5
commit a08043ae88
4 changed files with 40 additions and 25 deletions
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16
OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
View File

@ -57,14 +57,14 @@ class EmuTOS: public CPU::MC68000::BusHandler {
peripheral_result = 0x00000001;
break;
}
printf("Peripheral: %c %08x", (cycle.operation & Microcycle::Read) ? 'r' : 'w', *cycle.address);
if(!(cycle.operation & Microcycle::Read)) {
if(cycle.operation & Microcycle::SelectByte)
printf(" %02x", cycle.value->halves.low);
else
printf(" %04x", cycle.value->full);
}
printf("\n");
// printf("Peripheral: %c %08x", (cycle.operation & Microcycle::Read) ? 'r' : 'w', *cycle.address);
// if(!(cycle.operation & Microcycle::Read)) {
// if(cycle.operation & Microcycle::SelectByte)
// printf(" %02x", cycle.value->halves.low);
// else
// printf(" %04x", cycle.value->full);
// }
// printf("\n");
}
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {

4
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -74,20 +74,16 @@ class QL: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %04x] ", *cycle.address, cycle.value->full);
break;
case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %02x] ", *cycle.address, cycle.value->halves.low);
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
// if(!(cycle.operation & Microcycle::IsProgram)) printf("{%04x -> %08x} ", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
// if(!(cycle.operation & Microcycle::IsProgram)) printf("{%02x -> %08x} ", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}

43
Processors/68000/Implementation/68000Implementation.hpp
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@ -56,17 +56,17 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
// if(should_log) {
// std::cout << std::setfill('0');
// std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
// std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
// for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
// for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
// if(is_supervisor_) {
// std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
// } else {
// std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
// }
// std::cout << '\n';
std::cout << std::setfill('0');
std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
if(is_supervisor_) {
std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
} else {
std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
}
std::cout << '\n';
// }
decoded_instruction_ = prefetch_queue_.halves.high.full;
@ -76,7 +76,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
return;
} else {
// if(0x4f7a == program_counter_.full - 4) return;
// std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_ << '\t';
std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_ << '\t';
}
active_program_ = &instructions[decoded_instruction_];
@ -1377,6 +1377,25 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
active_step_->microcycle.length +
bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
if(!(active_step_->microcycle.operation & Microcycle::IsProgram)) {
switch(active_step_->microcycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
default: break;
case Microcycle::SelectWord | Microcycle::Read:
printf("[%08x -> %04x] ", *active_step_->microcycle.address, active_step_->microcycle.value->full);
break;
case Microcycle::SelectByte | Microcycle::Read:
printf("[%08x -> %02x] ", *active_step_->microcycle.address, active_step_->microcycle.value->halves.low);
break;
case Microcycle::SelectWord:
printf("{%04x -> %08x} ", active_step_->microcycle.value->full, *active_step_->microcycle.address);
break;
case Microcycle::SelectByte:
printf("{%02x -> %08x} ", active_step_->microcycle.value->halves.low, *active_step_->microcycle.address);
break;
}
}
/*
PERFORM THE BUS STEP'S ACTION.

2
Processors/68000/Implementation/68000Storage.cpp
View File

@ -2748,7 +2748,7 @@ struct ProcessorStorageConstructor {
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
op(Action::PerformOperation);
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }));
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
break;
case l2(Imm, XXXw): // MOVE.l #, (xxx).w