6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 08:31:11 +00:00
Code Issues Projects Releases Wiki Activity

Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.

Browse Source
This commit is contained in:
Thomas Harte 2017-06-19 22:07:36 -04:00
parent 6752f165db
commit a0d0f383c8
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Processors/Z80/Z80.hpp
View File

@ -656,7 +656,7 @@ template <class T> class Processor {
/* 0xc7 RST 00h */ RST(),
/* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ StdInstr(Pop(pc_)),
/* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */StdInstr(FINDEX(), {MicroOp::SetInstructionPage, &cb_page}),
/* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ StdInstr(Read16(pc_, temp16_), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}),
/* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ StdInstr(ReadInc(pc_, temp16_.bytes.low), Read4(pc_, temp16_.bytes.high), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}),
/* 0xce ADC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADC8, &temp8_}),
/* 0xcf RST 08h */ RST(),
/* 0xd0 RET NC */ RET(TestNC), /* 0xd1 POP DE */ StdInstr(Pop(de_)),