From a1f6f2c7f7c749c1f56f2fa011b3a6c1af2e230d Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Tue, 16 Jan 2024 22:42:20 -0500
Subject: [PATCH] Eliminate remaining macros.

---
 .../Implementation/6502Implementation.hpp     | 66 +++++++++----------
 1 file changed, 32 insertions(+), 34 deletions(-)

diff --git a/Processors/6502/Implementation/6502Implementation.hpp b/Processors/6502/Implementation/6502Implementation.hpp
index e815e73d5..6b6eb267a 100644
--- a/Processors/6502/Implementation/6502Implementation.hpp
+++ b/Processors/6502/Implementation/6502Implementation.hpp
@@ -71,6 +71,27 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 		bus_value_ = &val;
 	};
 
+	const auto push = [&](uint8_t &val) {
+		const uint16_t targetAddress = s_ | 0x100;
+		--s_;
+		write_mem(val, targetAddress);
+	};
+
+	const auto page_crossing_stall_read = [&] {
+		if(is_65c02(personality)) {
+			throwaway_read(pc_.full - 1);
+		} else {
+			throwaway_read(address_.full);
+		}
+	};
+
+	const auto bra = [&](bool condition) {
+		++pc_.full;
+		if(condition) {
+			scheduled_program_counter_ = operations_[size_t(OperationsSlot::DoBRA)];
+		}
+	};
+
 	while(number_of_cycles > Cycles(0)) {
 
 		// Deal with a potential RDY state, if this 6502 has anything connected to ready.
@@ -146,11 +167,6 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 						check_schedule();
 					continue;
 
-#define push(v) {\
-	uint16_t targetAddress = s_ | 0x100; s_--;\
-	write_mem(v, targetAddress);\
-}
-
 					case CycleIncPCPushPCH:				pc_.full++;														[[fallthrough]];
 					case CyclePushPCH:					push(pc_.halves.high);											break;
 					case CyclePushPCL:					push(pc_.halves.low);											break;
@@ -159,13 +175,12 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 					case CyclePushX:					push(x_);														break;
 					case CyclePushY:					push(y_);														break;
 					case CycleNoWritePush: {
-						uint16_t targetAddress = s_ | 0x100; s_--;
+						uint16_t targetAddress = s_ | 0x100;
+						--s_;
 						read_mem(operand_, targetAddress);
 					}
 					break;
 
-#undef push
-
 					case CycleReadFromS:				throwaway_read(s_ | 0x100);										break;
 					case CycleReadFromPC:				throwaway_read(pc_.full);										break;
 
@@ -555,13 +570,6 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 
 // MARK: - Addressing Mode Work
 
-#define page_crossing_stall_read()	\
-	if(is_65c02(personality)) {	\
-		throwaway_read(pc_.full - 1);	\
-	} else {	\
-		throwaway_read(address_.full);	\
-	}
-
 					case CycleAddXToAddressLow:
 						next_address_.full = address_.full + x_;
 						address_.halves.low = next_address_.halves.low;
@@ -579,8 +587,6 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 						}
 					continue;
 
-#undef page_crossing_stall_read
-
 					case CycleAddXToAddressLowRead:
 						next_address_.full = address_.full + x_;
 						address_.halves.low = next_address_.halves.low;
@@ -675,23 +681,15 @@ void Processor<personality, T, uses_ready_line>::run_for(const Cycles cycles) {
 
 // MARK: - Branching
 
-#define BRA(condition)	\
-	pc_.full++; \
-	if(condition) {	\
-		scheduled_program_counter_ = operations_[size_t(OperationsSlot::DoBRA)];	\
-	}
-
-					case OperationBPL: BRA(!(flags_.negative_result&0x80));			continue;
-					case OperationBMI: BRA(flags_.negative_result&0x80);			continue;
-					case OperationBVC: BRA(!flags_.overflow);						continue;
-					case OperationBVS: BRA(flags_.overflow);						continue;
-					case OperationBCC: BRA(!flags_.carry);							continue;
-					case OperationBCS: BRA(flags_.carry);							continue;
-					case OperationBNE: BRA(flags_.zero_result);						continue;
-					case OperationBEQ: BRA(!flags_.zero_result);					continue;
-					case OperationBRA: BRA(true);									continue;
-
-#undef BRA
+					case OperationBPL: bra(!(flags_.negative_result&0x80));			continue;
+					case OperationBMI: bra(flags_.negative_result&0x80);			continue;
+					case OperationBVC: bra(!flags_.overflow);						continue;
+					case OperationBVS: bra(flags_.overflow);						continue;
+					case OperationBCC: bra(!flags_.carry);							continue;
+					case OperationBCS: bra(flags_.carry);							continue;
+					case OperationBNE: bra(flags_.zero_result);						continue;
+					case OperationBEQ: bra(!flags_.zero_result);					continue;
+					case OperationBRA: bra(true);									continue;
 
 					case CycleAddSignedOperandToPC:
 						next_address_.full = uint16_t(pc_.full + int8_t(operand_));