From a2f01b4a4659339cf0ad3e2ff483b75b8983844e Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 4 Jun 2017 14:59:18 -0400
Subject: [PATCH] Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL)
 with the famous MEMPTR reliance is preventing a complete pass by Zexall now.

---
 Processors/Z80/Z80.hpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp
index bde44e87d..e39bc8ffc 100644
--- a/Processors/Z80/Z80.hpp
+++ b/Processors/Z80/Z80.hpp
@@ -1205,8 +1205,10 @@ template <class T> class Processor {
 	parity_overflow_result_ =  bc_.full ? Flag::Parity : 0;	\
 	half_carry_result_ = halfResult;	\
 	subtract_flag_ = Flag::Subtract;	\
+	sign_result_ = zero_result_ = result;	\
+	\
+	result -= (halfResult >> 4)&1;	\
 	bit53_result_ = (uint8_t)((result&0x8) | ((result&0x2) << 4));	\
-	sign_result_ = zero_result_ = result;
 
 						case MicroOp::CPDR: {
 							CPxR_STEP(-1);