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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-05 10:28:58 +00:00

Assuming I'm going to keep this synchronous, extends function signature.

This commit is contained in:
Thomas Harte 2021-07-26 20:13:06 -04:00
parent 1d03bc560a
commit a43175125a
3 changed files with 32 additions and 12 deletions

View File

@ -79,7 +79,7 @@ class ConcreteMachine:
cia_b_.run_for(e_clocks);
}
const auto changes = chipset_.run_for(cycle.length);
const auto changes = chipset_.run_for(cycle.length, false);
cia_a_.advance_tod(changes.vsyncs);
cia_b_.advance_tod(changes.hsyncs);
mc68000_.set_interrupt_level(changes.interrupt_level);

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@ -42,7 +42,7 @@ Chipset::Chipset(uint16_t *ram, size_t size) :
crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4) {
}
Chipset::Changes Chipset::run_for(HalfCycles length) {
Chipset::Changes Chipset::run_for(HalfCycles length, bool) {
Changes changes;
// Update raster position, spooling out something that isn't yet actual graphics.
@ -82,17 +82,35 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
const int final_x = x_ + line_pixels;
if(y_ < vertical_blank_height_) {
// Put three lines of sync at the centre of the vertical blank period.
// TODO: offset by half a line if interlaced.
// TODO: offset by half a line if interlaced and on an odd frame.
const int midline = vertical_blank_height_ >> 1;
if(y_ < midline - 1 || y_ > midline + 1) {
LINK(blank1, output_blank, blank1);
LINK(sync, output_sync, sync - blank1);
LINK(line_length_, output_blank, line_length_ - sync);
if(frame_height_ & 1) {
if(y_ < midline - 1 || y_ > midline + 2) {
LINK(blank1, output_blank, blank1);
LINK(sync, output_sync, sync - blank1);
LINK(line_length_, output_blank, line_length_ - sync);
} else if(y_ == midline - 1) {
LINK(113, output_blank, 113);
LINK(line_length_, output_sync, line_length_ - 113);
} else if(y_ == midline + 2) {
LINK(113, output_sync, 113);
LINK(line_length_, output_blank, line_length_ - 113);
} else {
LINK(blank1, output_sync, blank1);
LINK(sync, output_blank, sync - blank1);
LINK(line_length_, output_sync, line_length_ - sync);
}
} else {
LINK(blank1, output_sync, blank1);
LINK(sync, output_blank, sync - blank1);
LINK(line_length_, output_sync, line_length_ - sync);
if(y_ < midline - 1 || y_ > midline + 1) {
LINK(blank1, output_blank, blank1);
LINK(sync, output_sync, sync - blank1);
LINK(line_length_, output_blank, line_length_ - sync);
} else {
LINK(blank1, output_sync, blank1);
LINK(sync, output_blank, sync - blank1);
LINK(line_length_, output_sync, line_length_ - sync);
}
}
} else {
// Output the correct sequence of blanks, syncs and burst atomically.
@ -135,6 +153,7 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
#undef LINK
changes.interrupt_level = interrupt_level_;
changes.duration = length;
return changes;
}

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@ -31,10 +31,11 @@ class Chipset {
int hsyncs = 0;
int vsyncs = 0;
int interrupt_level = 0;
HalfCycles duration;
};
/// Advances the stated amount of time.
Changes run_for(HalfCycles);
/// Advances the stated amount of time, possibly stopping if a CPU slot is found.
Changes run_for(HalfCycles, bool stop_on_cpu_slot);
/// Performs the provided microcycle, which the caller guarantees to be a memory access.
void perform(const CPU::MC68000::Microcycle &);