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https://github.com/TomHarte/CLK.git
synced 2025-04-09 00:37:27 +00:00
Assuming I'm going to keep this synchronous, extends function signature.
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@ -79,7 +79,7 @@ class ConcreteMachine:
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cia_b_.run_for(e_clocks);
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}
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const auto changes = chipset_.run_for(cycle.length);
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const auto changes = chipset_.run_for(cycle.length, false);
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cia_a_.advance_tod(changes.vsyncs);
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cia_b_.advance_tod(changes.hsyncs);
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mc68000_.set_interrupt_level(changes.interrupt_level);
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@ -42,7 +42,7 @@ Chipset::Chipset(uint16_t *ram, size_t size) :
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4) {
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}
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Chipset::Changes Chipset::run_for(HalfCycles length) {
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Chipset::Changes Chipset::run_for(HalfCycles length, bool) {
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Changes changes;
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// Update raster position, spooling out something that isn't yet actual graphics.
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@ -82,17 +82,35 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
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const int final_x = x_ + line_pixels;
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if(y_ < vertical_blank_height_) {
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// Put three lines of sync at the centre of the vertical blank period.
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// TODO: offset by half a line if interlaced.
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// TODO: offset by half a line if interlaced and on an odd frame.
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const int midline = vertical_blank_height_ >> 1;
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if(y_ < midline - 1 || y_ > midline + 1) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_, output_blank, line_length_ - sync);
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if(frame_height_ & 1) {
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if(y_ < midline - 1 || y_ > midline + 2) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_, output_blank, line_length_ - sync);
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} else if(y_ == midline - 1) {
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LINK(113, output_blank, 113);
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LINK(line_length_, output_sync, line_length_ - 113);
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} else if(y_ == midline + 2) {
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LINK(113, output_sync, 113);
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LINK(line_length_, output_blank, line_length_ - 113);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_, output_sync, line_length_ - sync);
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}
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_, output_sync, line_length_ - sync);
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if(y_ < midline - 1 || y_ > midline + 1) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_, output_blank, line_length_ - sync);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_, output_sync, line_length_ - sync);
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}
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}
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} else {
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// Output the correct sequence of blanks, syncs and burst atomically.
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@ -135,6 +153,7 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
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#undef LINK
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changes.interrupt_level = interrupt_level_;
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changes.duration = length;
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return changes;
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}
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@ -31,10 +31,11 @@ class Chipset {
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int hsyncs = 0;
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int vsyncs = 0;
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int interrupt_level = 0;
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HalfCycles duration;
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};
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/// Advances the stated amount of time.
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Changes run_for(HalfCycles);
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/// Advances the stated amount of time, possibly stopping if a CPU slot is found.
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Changes run_for(HalfCycles, bool stop_on_cpu_slot);
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/// Performs the provided microcycle, which the caller guarantees to be a memory access.
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void perform(const CPU::MC68000::Microcycle &);
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