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Copies in notes for required test functions.
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@ -125,4 +125,107 @@ class MOS6522Tests: XCTestCase {
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XCTAssert($0.value(forRegister: 0) == 0x8a, "Data direction register should mix input and output; got \($0.value(forRegister: 0))")
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XCTAssert($0.value(forRegister: 0) == 0x8a, "Data direction register should mix input and output; got \($0.value(forRegister: 0))")
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}
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}
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}
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}
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func testShiftDisabled() {
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/*
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Mode 0 disables the Shift Register. In this mode the microprocessor can
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write or read the SR and the SR will shift on each CB1 positive edge
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shifting in the value on CB2. In this mode the SR Interrupt Flag is
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disabled (held to a logic 0).
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*/
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}
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func testShiftInUnderT2() {
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/*
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In mode 1, the shifting rate is controlled by the low order 8 bits of T2
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(Figure 22). Shift pulses are generated on the CB1 pin to control shifting
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in external devices. The time between transitions of this output clock is a
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function of the system clock period and the contents of the low order T2
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latch (N).
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The shifting operation is triggered by the read or write of the SR if the
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SR flag is set in the IFR. Otherwise the first shift will occur at the next
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time-out of T2 after a read or write of the SR. Data is shifted first into
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the low order bit of SR and is then shifted into the next higher order bit
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of the shift register on the negative-going edge of each clock pulse. The
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input data should change before the positive-going edge of the CB1 clock
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pulse. This data is shifted into shift register during the 02 clock cycle
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following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock
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pulses, the shift register interrupt flag will set and IRQ will go low.
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*/
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}
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func testShiftInUnderPhase2() {
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/*
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In mode 2, the shift rate is a direct function of the system clock
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frequency (Figure 23). CB1 becomes an output which generates shift pulses
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for controlling external devices. Timer 2 operates as an independent
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interval timer and has no effect on SR. The shifting operation is triggered
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by reading or writing the Shift Register. Data is shifted, first into bit 0
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and is then shifted into the next higher order bit of the shift register on
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the trailing edge of each 02 clock pulse. After 8 clock pulses, the shift
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register interrupt flag will be set, and the output clock pulses on CB1
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will stop.
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*/
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}
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func testShiftInUnderCB1() {
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/*
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In mode 3, external pin CB1 becomes an input (Figure 24). This allows an
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external device to load the shift register at its own pace. The shift
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register counter will interrupt the processor each time 8 bits have been
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shifted in. However the shift register counter does not stop the shifting
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operation; it acts simply as a pulse counter. Reading or writing the Shift
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Register resets the Interrupt Flag and initializes the SR counter to count
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another 8 pulses.
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Note that the data is shifted during the first system clock cycle
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following the positive-going edge of the CB1 shift pulse. For this reason,
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data must be held stable during the first full cycle following CB1 going
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high.
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*/
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}
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func testShiftOutUnderT2FreeRunning() {
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/*
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Mode 4 is very similar to mode 5 in which the shifting rate is set by T2.
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However, in mode 4 the SR Counter does not stop the shifting operation
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(Figure 25). Since the Shift Register bit 7 (SR7) is recirculated back into
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bit 0, the 8 bits loaded into the Shift Register will be clocked onto CB2
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repetitively. In this mode the Shift Register Counter is disabled.
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*/
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}
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func testShiftOutUnderT2() {
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/*
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In mode 5, the shift rate is controlled by T2 (as in mode 4). The shifting
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operation is triggered by the read or write of the SR if the SR flag is set
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in the IFR (Figure 26). Otherwise the first shift will occur at the next
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time-out of T2 after a read or write of the SR. However, with each read or
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write of the shift register the SR Counter is reset and 8 bits are shifted
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onto CB2. At the same time, 8 shift pulses are generated on CB1 to control
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shifting in external devices. After the 8 shift pulses, the shifting is
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disabled, the SR Interrupt Flag is set and CB2 remains at the last data
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level.
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*/
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}
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func testShiftOutUnderPhase2() {
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/*
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In mode 6, the shift rate is controlled by the 02 system clock (Figure 27).
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*/
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}
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func testShiftOutUnderCB1() {
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/*
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In mode 7, shifting is controlled by pulses applied to the CB1 pin by an
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external device (Figure 28). The SR counter sets the SR Interrupt Flag each
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time it counts 8 pulses but it does not disable the shifting function. Each
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time the microprocessor, writes or reads the shift register, the SR
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Interrupt Flag is reset and the SR counter is initialized to begin counting
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the next 8 shift pulses on pin CB1. After 8 shift pulses, the Interrupt
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Flag is set. The microprocessor can then load the shift register with the
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next byte of data.
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*/
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}
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}
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}
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