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https://github.com/TomHarte/CLK.git
synced 2024-07-06 01:28:57 +00:00
Started fleshing this out; addressing modes are completely decoded, along with a bunch of opcodes, but appropriate address advancement isn't in yet, and neither is filling in derived metadata.
This commit is contained in:
Thomas Harte
parent
f08e87c6c1
commit
a5fc45e66e
@ -7,18 +7,175 @@
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//
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#include "Disassembler6502.hpp"
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#include <map>
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using namespace StaticAnalyser::MOS6502;
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static void AddToDisassembly(const std::unique_ptr<Disassembly> &disassembly, uint16_t start_address, uint16_t entry_point)
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struct PartialDisassembly {
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Disassembly disassembly;
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std::vector<uint16_t> remaining_entry_points;
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};
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static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<uint8_t> &memory, uint16_t start_address, uint16_t entry_point)
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{
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uint16_t address = entry_point;
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while(1)
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{
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uint16_t local_address = address - start_address;
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if(local_address > memory.size()) return;
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address++;
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struct Instruction instruction;
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instruction.address = address;
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// get operation
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uint8_t operation = memory[local_address];
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// decode addressing mode
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switch(operation&0x1f)
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{
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case 0x00:
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if(operation >= 0x80) instruction.addressing_mode = Instruction::Immediate;
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else if(operation == 0x20) instruction.addressing_mode = Instruction::Absolute;
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else instruction.addressing_mode = Instruction::Implied;
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break;
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case 0x08: case 0x18: case 0x0a: case 0x1a: case 0x12:
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instruction.addressing_mode = Instruction::Implied;
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break;
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case 0x10:
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instruction.addressing_mode = Instruction::Relative;
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break;
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case 0x01: case 0x03:
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instruction.addressing_mode = Instruction::IndexedIndirectX;
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break;
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case 0x02: case 0x09: case 0x0b:
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instruction.addressing_mode = Instruction::Immediate;
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break;
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case 0x04: case 0x05: case 0x06: case 0x07:
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instruction.addressing_mode = Instruction::ZeroPage;
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break;
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case 0x0c: case 0x0d: case 0x0e: case 0x0f:
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instruction.addressing_mode = (operation == 0x6c) ? Instruction::Indirect : Instruction::Absolute;
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break;
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case 0x11: case 0x13:
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instruction.addressing_mode = Instruction::IndirectIndexedY;
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break;
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case 0x14: case 0x15: case 0x16: case 0x17:
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instruction.addressing_mode =
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(operation == 0x96 || operation == 0xb6 || operation == 0x97 || operation == 0xb7)
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? Instruction::ZeroPageY : Instruction::ZeroPageX;
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break;
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case 0x19: case 0x1b:
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instruction.addressing_mode = Instruction::AbsoluteY;
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break;
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case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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instruction.addressing_mode =
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(operation == 0x9e || operation == 0xbe || operation == 0x9f || operation == 0xbf)
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? Instruction::AbsoluteY : Instruction::AbsoluteX;
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break;
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}
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// decode operation
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#define RM_INSTRUCTION(base, op) \
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case base+0x09: case base+0x05: case base+0x15: case base+0x01: case base+0x11: case base+0x0d: case base+0x1d: case base+0x19: \
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instruction.operation = op; \
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break;
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#define M_INSTRUCTION(base, op) \
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case base+0x0a: case base+0x06: case base+0x16: case base+0x0e: case base+0x1e: \
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instruction.operation = op; \
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break;
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#define IM_INSTRUCTION(base, op) \
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case base: instruction.operation = op; break;
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switch(operation)
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{
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IM_INSTRUCTION(0x00, Instruction::BRK)
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IM_INSTRUCTION(0x40, Instruction::RTI)
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IM_INSTRUCTION(0x60, Instruction::RTS)
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IM_INSTRUCTION(0xca, Instruction::DEX)
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IM_INSTRUCTION(0x88, Instruction::DEY)
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IM_INSTRUCTION(0xe8, Instruction::INX)
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IM_INSTRUCTION(0xc8, Instruction::INY)
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IM_INSTRUCTION(0xaa, Instruction::TAX)
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IM_INSTRUCTION(0x8a, Instruction::TXA)
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IM_INSTRUCTION(0xa8, Instruction::TAY)
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IM_INSTRUCTION(0x98, Instruction::TYA)
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IM_INSTRUCTION(0xba, Instruction::TSX)
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IM_INSTRUCTION(0x9a, Instruction::TXS)
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IM_INSTRUCTION(0x68, Instruction::PLA)
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IM_INSTRUCTION(0x48, Instruction::PHA)
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IM_INSTRUCTION(0x28, Instruction::PLP)
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IM_INSTRUCTION(0x08, Instruction::PHP)
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IM_INSTRUCTION(0x18, Instruction::CLC)
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IM_INSTRUCTION(0x38, Instruction::SEC)
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IM_INSTRUCTION(0xd8, Instruction::CLD)
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IM_INSTRUCTION(0xf8, Instruction::SED)
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IM_INSTRUCTION(0x58, Instruction::CLI)
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IM_INSTRUCTION(0x78, Instruction::SEI)
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IM_INSTRUCTION(0xb8, Instruction::CLV)
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RM_INSTRUCTION(0x00, Instruction::ORA)
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RM_INSTRUCTION(0x20, Instruction::AND)
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RM_INSTRUCTION(0x40, Instruction::EOR)
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RM_INSTRUCTION(0x60, Instruction::ADC)
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RM_INSTRUCTION(0xc0, Instruction::CMP)
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RM_INSTRUCTION(0xe0, Instruction::SBC)
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M_INSTRUCTION(0x00, Instruction::ASL)
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M_INSTRUCTION(0x20, Instruction::ROL)
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M_INSTRUCTION(0x40, Instruction::LSR)
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M_INSTRUCTION(0x60, Instruction::ROR)
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case 0xe0: case 0xe4: case 0xec: instruction.operation = Instruction::CPX; break;
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case 0xc0: case 0xc4: case 0xcc: instruction.operation = Instruction::CPY; break;
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case 0xc6: case 0xd6: case 0xce: case 0xde: instruction.operation = Instruction::DEC; break;
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case 0xe6: case 0xf6: case 0xee: case 0xfe: instruction.operation = Instruction::INC; break;
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RM_INSTRUCTION(0xa0, Instruction::LDA)
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case 0x85: case 0x95: case 0x81: case 0x91: case 0x8d: case 0x9d: case 0x99:
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instruction.operation = Instruction::STA;
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break;
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case 0xa2: case 0xa6: case 0xb6: case 0xae: case 0xbe:
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instruction.operation = Instruction::LDX;
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break;
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case 0x86: case 0x96: case 0x8e:
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instruction.operation = Instruction::STX;
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break;
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case 0xa0: case 0xa4: case 0xb4: case 0xac: case 0xbc:
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instruction.operation = Instruction::LDY;
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break;
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case 0x84: case 0x94: case 0x8c:
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instruction.operation = Instruction::STY;
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break;
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}
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disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
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}
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}
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std::unique_ptr<Disassembly> Disassemble(std::vector<uint8_t> memory, uint16_t start_address, std::vector<uint16_t> entry_points)
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Disassembly Disassemble(const std::vector<uint8_t> &memory, uint16_t start_address, std::vector<uint16_t> entry_points)
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{
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std::unique_ptr<Disassembly> disassembly;
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PartialDisassembly partialDisassembly;
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partialDisassembly.remaining_entry_points = entry_points;
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while(!partialDisassembly.remaining_entry_points.empty())
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{
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// pull the next entry point from the back of the vector
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uint16_t next_entry_point = partialDisassembly.remaining_entry_points.back();
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partialDisassembly.remaining_entry_points.pop_back();
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// if that address has already bene visited, forget about it
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if(partialDisassembly.disassembly.instructions_by_address.find(next_entry_point) != partialDisassembly.disassembly.instructions_by_address.end()) continue;
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return disassembly;
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// otherwise perform a diassembly run
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AddToDisassembly(partialDisassembly, memory, start_address, next_entry_point);
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}
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return std::move(partialDisassembly.disassembly);
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}
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@ -13,6 +13,7 @@
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#include <memory>
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#include <set>
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#include <vector>
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#include <map>
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namespace StaticAnalyser {
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namespace MOS6502 {
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@ -20,22 +21,50 @@ namespace MOS6502 {
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struct Instruction {
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uint16_t address;
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enum {
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BRK, ORA, KIL, SLO, NOP, ASL, PHP, ANC, BPL
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BRK, RTI, RTS,
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CLC, SEC, CLD, SED, CLI, SEI, CLV,
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NOP,
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KIL, SLO, ANC,
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AND, EOR, ORA,
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ADC, SBC,
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LDA, STA, LDX, STX, LDY, STY,
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BPL, BMI, BVC, BVS, BCC, BCS, BNE, BEQ,
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CMP, CPX, CPY,
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INC, DEC, DEX, DEY, INX, INY,
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ASL, ROL, LSR, ROR,
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TAX, TXA, TAY, TYA, TSX, TXS,
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PLA, PHA, PLP, PHP
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} operation;
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enum {
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Absolute, AbsoluteIndirect, Accumulator,
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Immediate, Implied, IndexAbsolute, IndexedZeroPage,
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IndexedIndirectX, IndirectIndexedY, Relative, ZeroPage
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Absolute,
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AbsoluteX,
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AbsoluteY,
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AbsoluteIndirect,
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Accumulator,
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Immediate,
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Implied,
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ZeroPage,
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ZeroPageX,
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ZeroPageY,
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Indirect,
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IndexedIndirectX,
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IndirectIndexedY,
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Relative,
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} addressing_mode;
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uint16_t operand;
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};
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struct Disassembly {
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std::vector<Instruction> instructions;
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std::map<uint16_t, Instruction> instructions_by_address;
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std::set<uint16_t> outward_calls;
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std::set<uint16_t> external_stores, external_loads, external_modifies;
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};
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std::unique_ptr<Disassembly> Disassemble(std::vector<uint8_t> memory, uint16_t start_address, std::vector<uint16_t> entry_points);
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Disassembly Disassemble(const std::vector<uint8_t> &memory, uint16_t start_address, std::vector<uint16_t> entry_points);
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}
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}
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