From a8f41b9017c13f09d36418714fdc1ac0ea14d659 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 22 Oct 2025 17:48:19 -0400
Subject: [PATCH] Implement RTI and RTS.

---
 Processors/6502Mk2/Implementation/6502.hpp | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Processors/6502Mk2/Implementation/6502.hpp b/Processors/6502Mk2/Implementation/6502.hpp
index 23cab3c8f..971c7d66a 100644
--- a/Processors/6502Mk2/Implementation/6502.hpp
+++ b/Processors/6502Mk2/Implementation/6502.hpp
@@ -594,6 +594,27 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
 
 			goto fetch_decode;
 
+		case access_program(RTI):
+			access(BusOperation::Read, Stack(registers.s), Storage::operand_);
+
+			access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
+			registers.flags = Flags(Storage::operand_);
+
+			access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
+			check_interrupt();
+			access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
+
+			goto fetch_decode;
+
+		case access_program(RTS):
+			access(BusOperation::Read, Stack(registers.s), Storage::operand_);
+
+			access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
+			check_interrupt();
+			access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
+			++registers.pc.full;
+
+			goto fetch_decode;
 
 		// MARK: - NMI/IRQ/Reset, and BRK.