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Implement RTI and RTS.
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@@ -594,6 +594,27 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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case access_program(RTI):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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registers.flags = Flags(Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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goto fetch_decode;
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case access_program(RTS):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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++registers.pc.full;
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goto fetch_decode;
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// MARK: - NMI/IRQ/Reset, and BRK.
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