From aac2f7dd733ea48a9b9f8393e4193f9ee40c0593 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 8 Apr 2022 09:47:04 -0400
Subject: [PATCH] Add missing validations.
---
InstructionSets/PowerPC/Decoder.cpp | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/InstructionSets/PowerPC/Decoder.cpp b/InstructionSets/PowerPC/Decoder.cpp
index a4de269f0..ca73462d9 100644
--- a/InstructionSets/PowerPC/Decoder.cpp
+++ b/InstructionSets/PowerPC/Decoder.cpp
@@ -21,6 +21,8 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
// Otherwise, validation depends on operation
// (and, in principle, processor model).
switch(operation) {
+ case Operation::absx: case Operation::clcs:
+ case Operation::nabsx:
case Operation::addmex: case Operation::addzex:
case Operation::bcctrx: case Operation::bclrx:
case Operation::cntlzdx: case Operation::cntlzwx:
@@ -143,10 +145,18 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
break;
- case Operation::mtsrin:
+ case Operation::mtsrin: case Operation::mfsrin:
if(opcode & 0b000000'00000'11111'00000'0000000000'1) return Instruction(opcode);
break;
+ case Operation::mfsr:
+ if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
+ break;
+
+ case Operation::mtcrf:
+ if(opcode & 0b000000'00000'10000'00001'0000000000'1) return Instruction(opcode);
+ break;
+
case Operation::mulhdx: case Operation::mulhdux:
case Operation::mulhwx: case Operation::mulhwux:
if(opcode & 0b000000'00000'00000'00000'1000000000'0) return Instruction(opcode);
@@ -165,10 +175,19 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
if(!(opcode & 0b000000'00000'00000'00000'0000000000'1)) return Instruction(opcode);
break;
- case Operation::clcs:
- if(opcode & 0b000000'00000'00000'11111'0000000000'1) return Instruction(opcode);
- break;
-
+ case Operation::divx: case Operation::divsx:
+ case Operation::dozx: case Operation::dozi:
+ case Operation::lscbxx:
+ case Operation::maskgx: case Operation::maskirx:
+ case Operation::mulx:
+ case Operation::rlmix: case Operation::rribx:
+ case Operation::slex: case Operation::sleqx: case Operation::sliqx:
+ case Operation::slliqx: case Operation::sllqx: case Operation::slqx:
+ case Operation::sraiqx: case Operation::sraqx:
+ case Operation::srex: case Operation::sreqx:
+ case Operation::sriqx: case Operation::srliqx:
+ case Operation::srlqx: case Operation::srqx:
+ case Operation::sreax:
case Operation::addx: case Operation::addcx: case Operation::addex:
case Operation::addi: case Operation::addic: case Operation::addic_:
case Operation::addis: