6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-02-06 13:31:55 +00:00
Code Issues Projects Releases Wiki Activity

Attempts to consolidate source/destination ordering.

Browse Source
This commit is contained in:
Thomas Harte 2021-01-03 17:28:29 -05:00
parent 11b6c1d4b5
commit adcb2e03e8
2 changed files with 27 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Processors/Decoders/x86/x86.cpp
View File

@ -17,7 +17,6 @@ using namespace CPU::Decoder::x86;
Decoder::Decoder(Model) {}
Instruction Decoder::decode(uint8_t *source, size_t length) {
uint8_t *const begin = source;
uint8_t *const end = source + length;
#define MapPartial(value, op, lrg, fmt, phs) \
@ -42,6 +41,10 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
// to the ModRM byte.
instr_ = *source;
switch(instr_) {
default:
reset_parsing();
return Instruction();
#define PartialBlock(start, operation) \
MapPartial(start + 0x00, operation, false, MemReg_Reg, ModRM); \
MapPartial(start + 0x01, operation, true, MemReg_Reg, ModRM); \
@ -220,13 +223,9 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
case 3: memreg = reg_table[large_operand_][rm]; break;
}
if(format_ == Format::Reg_MemReg) {
destination_ = reg_table[large_operand_][reg];
source_ = memreg;
} else {
source_ = reg_table[large_operand_][reg];
destination_ = memreg;
}
// These will be switched over at ReadyToPost if the format_ requires it.
source_ = reg_table[large_operand_][reg];
destination_ = memreg;
phase_ = (add_offset_ || memreg == Source::DirectAddress) ? Phase::AwaitingOperands : Phase::ReadyToPost;
} break;
@ -273,12 +272,19 @@ Instruction Decoder::decode(uint8_t *source, size_t length) {
result = Instruction(operation_, large_operand_ ? Size::Word : Size::Byte, source_, destination_, consumed_);
break;
default: break;
case Format::MemReg_Reg:
result = Instruction(operation_, large_operand_ ? Size::Word : Size::Byte, source_, destination_, consumed_);
break;
case Format::Reg_MemReg:
result = Instruction(operation_, large_operand_ ? Size::Word : Size::Byte, destination_, source_, consumed_);
break;
default: assert(false);
}
// Reset parser.
consumed_ = operand_bytes_ = 0;
lock_ = add_offset_ = large_offset_ = false;
reset_parsing();
phase_ = Phase::Instruction;
return result;

14
Processors/Decoders/x86/x86.hpp
View File

@ -140,17 +140,23 @@ struct Decoder {
None, RepE, RepNE
} repetition_ = Repetition::None;
int consumed_ = 0;
int operand_bytes_ = 0;
Operation operation_ = Operation::Invalid;
bool large_operand_ = false;
Source source_ = Source::None;
Source destination_ = Source::None;
Source segment_override_ = Source::None;
uint8_t instr_ = 0x00;
bool lock_ = false;
bool add_offset_ = false;
bool large_offset_ = false;
int consumed_ = 0;
int operand_bytes_ = 0;
bool lock_ = false;
Source segment_override_ = Source::None;
void reset_parsing() {
consumed_ = operand_bytes_ = 0;
lock_ = false;
segment_override_ = Source::None;
}
};
}