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https://github.com/TomHarte/CLK.git
synced 2025-01-29 20:31:46 +00:00
Formally decode bank/offset/type.
This commit is contained in:
Thomas Harte
parent
fa0a9aa611
commit
ae684edbe1
@ -113,87 +113,110 @@ struct InputOutputController {
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}
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}
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static constexpr uint32_t AddressMask = 0x1f'ffff;
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/// Decomposes an Archimedes bus address into bank, offset and type.
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struct Address {
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constexpr Address(uint32_t bus_address) noexcept {
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bank = (bus_address >> 16) & 0b111;
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type = Type((bus_address >> 19) & 0b11);
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offset = bus_address & 0b1111100;
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}
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/// A value from 0 to 7 indicating the device being addressed.
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uint32_t bank;
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/// A seven-bit value which is a multiple of 4, indicating the address within the bank.
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uint32_t offset;
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/// Access type.
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enum class Type {
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Sync = 0b00,
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Fast = 0b01,
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Medium = 0b10,
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Slow = 0b11
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} type;
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};
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bool read(uint32_t address, uint8_t &value) {
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const auto target = address & AddressMask;
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const Address target(address);
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value = 0xff;
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switch(target) {
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switch(target.bank) {
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default:
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logger.error().append("Unrecognised IOC read from %08x", address);
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logger.error().append("Unrecognised IOC read from %08x i.e. bank %d / type %d", address, target.bank, target.type);
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break;
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case 0x3200000 & AddressMask:
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value = control_ | 0xc0;
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value &= ~(i2c_.clock() ? 2 : 0);
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value &= ~(i2c_.data() ? 1 : 0);
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// logger.error().append("IOC control read: C:%d D:%d", !(value & 2), !(value & 1));
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return true;
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// Bank 0: internal registers.
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case 0:
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switch(target.offset) {
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default:
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logger.error().append("Unrecognised IOC bank 0 read; offset %02x", target.offset);
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break;
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case 0x3200004 & AddressMask:
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value = serial_.input(IOCParty);
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irq_b_.clear(IRQB::KeyboardReceiveFull);
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observer_.update_interrupts();
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// logger.error().append("IOC keyboard receive: %02x", value);
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return true;
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case 0x00:
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value = control_ | 0xc0;
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value &= ~(i2c_.clock() ? 2 : 0);
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value &= ~(i2c_.data() ? 1 : 0);
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// logger.error().append("IOC control read: C:%d D:%d", !(value & 2), !(value & 1));
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break;
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// IRQ A.
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case 0x3200010 & AddressMask:
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value = irq_a_.status;
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// logger.error().append("IRQ A status is %02x", value);
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return true;
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case 0x3200014 & AddressMask:
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value = irq_a_.request();
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// logger.error().append("IRQ A request is %02x", value);
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return true;
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case 0x3200018 & AddressMask:
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value = irq_a_.mask;
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// logger.error().append("IRQ A mask is %02x", value);
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return true;
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case 0x04:
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value = serial_.input(IOCParty);
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irq_b_.clear(IRQB::KeyboardReceiveFull);
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observer_.update_interrupts();
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// logger.error().append("IOC keyboard receive: %02x", value);
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break;
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// IRQ B.
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case 0x3200020 & AddressMask:
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value = irq_b_.status;
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// logger.error().append("IRQ B status is %02x", value);
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return true;
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case 0x3200024 & AddressMask:
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value = irq_b_.request();
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// logger.error().append("IRQ B request is %02x", value);
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return true;
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case 0x3200028 & AddressMask:
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value = irq_b_.mask;
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// logger.error().append("IRQ B mask is %02x", value);
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return true;
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// IRQ A.
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case 0x10:
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value = irq_a_.status;
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// logger.error().append("IRQ A status is %02x", value);
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break;
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case 0x14:
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value = irq_a_.request();
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// logger.error().append("IRQ A request is %02x", value);
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break;
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case 0x18:
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value = irq_a_.mask;
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// logger.error().append("IRQ A mask is %02x", value);
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break;
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// FIQ.
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case 0x3200030 & AddressMask:
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value = fiq_.status;
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logger.error().append("FIQ status is %02x", value);
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return true;
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case 0x3200034 & AddressMask:
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value = fiq_.request();
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logger.error().append("FIQ request is %02x", value);
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return true;
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case 0x3200038 & AddressMask:
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value = fiq_.mask;
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logger.error().append("FIQ mask is %02x", value);
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return true;
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// IRQ B.
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case 0x20:
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value = irq_b_.status;
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// logger.error().append("IRQ B status is %02x", value);
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break;
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case 0x24:
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value = irq_b_.request();
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// logger.error().append("IRQ B request is %02x", value);
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break;
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case 0x28:
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value = irq_b_.mask;
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// logger.error().append("IRQ B mask is %02x", value);
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break;
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// Counters.
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case 0x3200040 & AddressMask:
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case 0x3200050 & AddressMask:
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case 0x3200060 & AddressMask:
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case 0x3200070 & AddressMask:
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value = counters_[(target >> 4) - 0x4].output & 0xff;
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// logger.error().append("%02x: Counter %d low is %02x", target, (target >> 4) - 0x4, value);
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return true;
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// FIQ.
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case 0x30:
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value = fiq_.status;
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logger.error().append("FIQ status is %02x", value);
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break;
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case 0x34:
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value = fiq_.request();
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logger.error().append("FIQ request is %02x", value);
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break;
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case 0x38:
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value = fiq_.mask;
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logger.error().append("FIQ mask is %02x", value);
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break;
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case 0x3200044 & AddressMask:
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case 0x3200054 & AddressMask:
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case 0x3200064 & AddressMask:
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case 0x3200074 & AddressMask:
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value = counters_[(target >> 4) - 0x4].output >> 8;
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// logger.error().append("%02x: Counter %d high is %02x", target, (target >> 4) - 0x4, value);
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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value = counters_[(target.offset >> 4) - 0x4].output & 0xff;
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// logger.error().append("%02x: Counter %d low is %02x", target, (target >> 4) - 0x4, value);
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break;
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case 0x44: case 0x54: case 0x64: case 0x74:
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value = counters_[(target.offset >> 4) - 0x4].output >> 8;
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// logger.error().append("%02x: Counter %d high is %02x", target, (target >> 4) - 0x4, value);
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break;
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}
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return true;
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}
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@ -201,113 +224,109 @@ struct InputOutputController {
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}
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bool write(uint32_t address, uint8_t value) {
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const auto target = address & AddressMask;
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switch(target) {
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const Address target(address);
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switch(target.bank) {
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default:
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logger.error().append("Unrecognised IOC write of %02x at %08x", value, address);
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logger.error().append("Unrecognised IOC write of %02x to %08x i.e. bank %d / type %d", value, address, target.bank, target.type);
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break;
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case 0x320'0000 & AddressMask:
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// TODO: does the rest of the control register relate to anything?
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control_ = value;
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i2c_.set_clock_data(!(value & 2), !(value & 1));
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return true;
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// Bank 0: internal registers.
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case 0:
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switch(target.offset) {
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default:
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logger.error().append("Unrecognised IOC bank 0 write; %02x to offset %02x", value, target.offset);
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break;
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case 0x320'0004 & AddressMask:
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serial_.output(IOCParty, value);
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irq_b_.clear(IRQB::KeyboardTransmitEmpty);
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observer_.update_interrupts();
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return true;
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case 0x00:
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// TODO: does the rest of the control register relate to anything?
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control_ = value;
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i2c_.set_clock_data(!(value & 2), !(value & 1));
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break;
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case 0x320'0014 & AddressMask:
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// b2: clear IF.
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// b3: clear IR.
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// b4: clear POR.
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// b5: clear TM[0].
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// b6: clear TM[1].
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irq_a_.clear(value & 0x7c);
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observer_.update_interrupts();
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return true;
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case 0x04:
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serial_.output(IOCParty, value);
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irq_b_.clear(IRQB::KeyboardTransmitEmpty);
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observer_.update_interrupts();
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break;
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// Interrupts.
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case 0x320'0018 & AddressMask: irq_a_.mask = value; return true;
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case 0x320'0028 & AddressMask: irq_b_.mask = value; return true;
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case 0x320'0038 & AddressMask: fiq_.mask = value; return true;
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case 0x14:
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// b2: clear IF.
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// b3: clear IR.
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// b4: clear POR.
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// b5: clear TM[0].
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// b6: clear TM[1].
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irq_a_.clear(value & 0x7c);
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observer_.update_interrupts();
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break;
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// Counters.
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case 0x320'0040 & AddressMask:
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case 0x320'0050 & AddressMask:
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case 0x320'0060 & AddressMask:
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case 0x320'0070 & AddressMask:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0xff00) | value
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);
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return true;
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// Interrupts.
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case 0x18: irq_a_.mask = value; break;
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case 0x28: irq_b_.mask = value; break;
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case 0x38: fiq_.mask = value; break;
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case 0x320'0044 & AddressMask:
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case 0x320'0054 & AddressMask:
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case 0x320'0064 & AddressMask:
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case 0x320'0074 & AddressMask:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0x00ff) | (value << 8)
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);
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return true;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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counters_[(target.offset >> 4) - 0x4].reload = uint16_t(
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(counters_[(target.offset >> 4) - 0x4].reload & 0xff00) | value
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);
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break;
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case 0x320'0048 & AddressMask:
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case 0x320'0058 & AddressMask:
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case 0x320'0068 & AddressMask:
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case 0x320'0078 & AddressMask:
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counters_[(target >> 4) - 0x4].value = counters_[(target >> 4) - 0x4].reload;
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return true;
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case 0x44: case 0x54: case 0x64: case 0x74:
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counters_[(target.offset >> 4) - 0x4].reload = uint16_t(
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(counters_[(target.offset >> 4) - 0x4].reload & 0x00ff) | (value << 8)
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);
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break;
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case 0x320'004c & AddressMask:
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case 0x320'005c & AddressMask:
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case 0x320'006c & AddressMask:
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case 0x320'007c & AddressMask:
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counters_[(target >> 4) - 0x4].output = counters_[(target >> 4) - 0x4].value;
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return true;
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case 0x48: case 0x58: case 0x68: case 0x78:
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counters_[(target.offset >> 4) - 0x4].value = counters_[(target.offset >> 4) - 0x4].reload;
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break;
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case 0x327'0000 & AddressMask:
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logger.error().append("TODO: exteded external podule space");
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return true;
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case 0x331'0000 & AddressMask:
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logger.error().append("TODO: 1772 / disk write");
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return true;
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case 0x335'0000 & AddressMask:
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logger.error().append("TODO: LS374 / printer data write");
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return true;
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case 0x335'0018 & AddressMask:
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logger.error().append("TODO: latch B write: %02x", value);
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return true;
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case 0x335'0040 & AddressMask:
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logger.error().append("TODO: latch A write: %02x", value);
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return true;
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case 0x335'0048 & AddressMask:
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logger.error().append("TODO: latch C write: %02x", value);
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return true;
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case 0x336'0000 & AddressMask:
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logger.error().append("TODO: podule interrupt request");
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return true;
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case 0x336'0004 & AddressMask:
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logger.error().append("TODO: podule interrupt mask");
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return true;
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case 0x33a'0000 & AddressMask:
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logger.error().append("TODO: 6854 / econet write");
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return true;
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case 0x33b'0000 & AddressMask:
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logger.error().append("TODO: 6551 / serial line write");
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return true;
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case 0x4c: case 0x5c: case 0x6c: case 0x7c:
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counters_[(target.offset >> 4) - 0x4].output = counters_[(target.offset >> 4) - 0x4].value;
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break;
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}
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return true;
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}
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// case 0x327'0000 & AddressMask: // Bank 7
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// logger.error().append("TODO: exteded external podule space");
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// return true;
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//
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// case 0x331'0000 & AddressMask:
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// logger.error().append("TODO: 1772 / disk write");
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// return true;
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//
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// case 0x335'0000 & AddressMask:
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// logger.error().append("TODO: LS374 / printer data write");
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// return true;
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//
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// case 0x335'0018 & AddressMask:
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// logger.error().append("TODO: latch B write: %02x", value);
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// return true;
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//
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// case 0x335'0040 & AddressMask:
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// logger.error().append("TODO: latch A write: %02x", value);
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// return true;
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//
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// case 0x335'0048 & AddressMask:
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// logger.error().append("TODO: latch C write: %02x", value);
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// return true;
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//
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// case 0x336'0000 & AddressMask:
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// logger.error().append("TODO: podule interrupt request");
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// return true;
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//
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// case 0x336'0004 & AddressMask:
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// logger.error().append("TODO: podule interrupt mask");
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// return true;
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//
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// case 0x33a'0000 & AddressMask:
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// logger.error().append("TODO: 6854 / econet write");
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// return true;
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//
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// case 0x33b'0000 & AddressMask:
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// logger.error().append("TODO: 6551 / serial line write");
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// return true;
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return true;
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}
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