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Imports AND tests.
This commit is contained in:
Thomas Harte
parent
eedf7358b4
commit
aff40bf00a
@ -194,6 +194,361 @@
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// Omitted: address error test.
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- (void)testANDl_PreDec {
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_machine->set_program({
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0xc6a4 // AND.l -(A4), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3004;
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*_machine->ram_at(0x3000) = 0x0053;
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*_machine->ram_at(0x3002) = 0xfb00;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
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XCTAssertEqual(state.address[4], 0x3000);
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XCTAssertEqual(state.data[3], 0x0053f800);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(16, _machine->get_cycle_count());
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}
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- (void)testANDl_d16An {
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_machine->set_program({
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0xc6ac, 0xfffa // AND.l -6(A4), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3006;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
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XCTAssertEqual(state.address[4], 0x3006);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(18, _machine->get_cycle_count());
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}
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- (void)testANDl_d8AnDnw_positive {
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_machine->set_program({
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0xc6b4, 0x6006 // AND.l 6(A4, D6.W), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[6] = 0xfffffffd;
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state.address[4] = 0x2ffd;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
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XCTAssertEqual(state.address[4], 0x2ffd);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.data[6], 0xfffffffd);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDl_d8AnDnw_negative {
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_machine->set_program({
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0xc6b4, 0x60fe // AND.l -2(A4, D6.W), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[6] = 0xf001fffd;
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state.address[4] = 0x3005;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
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XCTAssertEqual(state.address[4], 0x3005);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.data[6], 0xf001fffd);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDl_d8AnDnl {
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_machine->set_program({
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0xc6b4, 0x6801 // AND.l 6(A4, D6.W), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[6] = 0xffffffff;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
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XCTAssertEqual(state.address[4], 0x3000);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.data[6], 0xffffffff);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDl_XXXw {
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_machine->set_program({
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0xc6b8, 0x3000 // AND.l $3000.w, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(18, _machine->get_cycle_count());
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}
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- (void)testANDl_XXXl {
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_machine->set_program({
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0xc6b9, 0x0001, 0x1170 // AND.L $11170.l, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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*_machine->ram_at(0x11170) = 0x1253;
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*_machine->ram_at(0x11172) = 0xfb34;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x11170), 0x1253);
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XCTAssertEqual(*_machine->ram_at(0x11172), 0xfb34);
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XCTAssertEqual(state.data[3], 0x1053f814);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(22, _machine->get_cycle_count());
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}
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- (void)testANDl_d16PC {
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_machine->set_program({
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0xc6ba, 0xfffa // AND.l -6(PC), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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*_machine->ram_at(0xffc) = 0x383c;
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*_machine->ram_at(0xffe) = 0x1234;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
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XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
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XCTAssertEqual(state.data[3], 0x103c1014);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(18, _machine->get_cycle_count());
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}
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- (void)testANDl_d8AnPC {
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_machine->set_program({
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0xc6bb, 0x10f6 // and.l -10(PC), D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[1] = 4;
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*_machine->ram_at(0xffc) = 0x383c;
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*_machine->ram_at(0xffe) = 0x1234;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
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XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
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XCTAssertEqual(state.data[3], 0x103c1014);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDb_Imm {
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_machine->set_program({
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0xc63c, 0x0034 // AND.b #$34, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff814);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(8, _machine->get_cycle_count());
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}
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- (void)testANDw_Imm {
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_machine->set_program({
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0xc67c, 0x1234 // AND.w #$1234, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54ff1014);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(8, _machine->get_cycle_count());
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}
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- (void)testANDl_Imm {
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_machine->set_program({
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0xc6bc, 0x3456, 0x1234 // AND.l #$34561234, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x14561014);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(16, _machine->get_cycle_count());
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}
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- (void)testANDl_IndTarget {
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_machine->set_program({
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0xc794 // AND.l D3, (A4)
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb03;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff856);
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XCTAssertEqual(state.address[4], 0x3000);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDl_PostIncTarget {
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_machine->set_program({
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0xc79c // AND.l D3, (A4)+
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb03;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff856);
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XCTAssertEqual(state.address[4], 0x3004);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testANDl_PreDecTarget {
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_machine->set_program({
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0xc7a4 // AND.l D3, -(A4)
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x2ffc) = 0x1253;
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*_machine->ram_at(0x2ffe) = 0xfb03;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff856);
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XCTAssertEqual(state.address[4], 0x2ffc);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(*_machine->ram_at(0x2ffc), 0x1053);
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XCTAssertEqual(*_machine->ram_at(0x2ffe), 0xf802);
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XCTAssertEqual(22, _machine->get_cycle_count());
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}
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- (void)testANDl_d16AnTarget {
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_machine->set_program({
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0xc7ac, 0x0002 // AND.l D3, 2(A4)
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3002) = 0x1253;
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*_machine->ram_at(0x3004) = 0xfb03;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff856);
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XCTAssertEqual(state.address[4], 0x3000);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0x1053);
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XCTAssertEqual(*_machine->ram_at(0x3004), 0xf802);
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XCTAssertEqual(24, _machine->get_cycle_count());
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}
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- (void)testANDl_xxxWTarget {
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_machine->set_program({
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0xc7b8, 0x3000 // AND.l D3, ($3000).w
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x1253;
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*_machine->ram_at(0x3002) = 0xfb03;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff856);
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XCTAssertEqual(state.address[4], 0x3000);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
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XCTAssertEqual(24, _machine->get_cycle_count());
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}
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// MARK: BCHG
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- (void)performBCHGD0D1:(uint32_t)d1 {
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