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Adds a type for the operation bitfield.
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@ -49,51 +49,53 @@ namespace MC68000 {
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avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
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avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
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*/
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*/
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struct Microcycle {
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struct Microcycle {
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using OperationT = unsigned int;
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/// Indicates that the address strobe and exactly one of the data strobes are active; you can determine
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/// Indicates that the address strobe and exactly one of the data strobes are active; you can determine
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/// which by inspecting the low bit of the provided address. The RW line indicates a read.
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/// which by inspecting the low bit of the provided address. The RW line indicates a read.
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static constexpr int SelectByte = 1 << 0;
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static constexpr OperationT SelectByte = 1 << 0;
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// Maintenance note: this is bit 0 to reduce the cost of getting a host-endian
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// Maintenance note: this is bit 0 to reduce the cost of getting a host-endian
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// bytewise address. The assumption that it is bit 0 is also used for branchless
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// bytewise address. The assumption that it is bit 0 is also used for branchless
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// selection in a few places. See implementation of host_endian_byte_address(),
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// selection in a few places. See implementation of host_endian_byte_address(),
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// value8_high(), value8_low() and value16().
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// value8_high(), value8_low() and value16().
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/// Indicates that the address and both data select strobes are active.
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/// Indicates that the address and both data select strobes are active.
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static constexpr int SelectWord = 1 << 1;
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static constexpr OperationT SelectWord = 1 << 1;
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/// A NewAddress cycle is one in which the address strobe is initially low but becomes high;
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/// A NewAddress cycle is one in which the address strobe is initially low but becomes high;
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/// this correlates to states 0 to 5 of a standard read/write cycle.
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/// this correlates to states 0 to 5 of a standard read/write cycle.
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static constexpr int NewAddress = 1 << 2;
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static constexpr OperationT NewAddress = 1 << 2;
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/// A SameAddress cycle is one in which the address strobe is continuously asserted, but neither
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/// A SameAddress cycle is one in which the address strobe is continuously asserted, but neither
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/// of the data strobes are.
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/// of the data strobes are.
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static constexpr int SameAddress = 1 << 3;
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static constexpr OperationT SameAddress = 1 << 3;
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/// A Reset cycle is one in which the RESET output is asserted.
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/// A Reset cycle is one in which the RESET output is asserted.
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static constexpr int Reset = 1 << 4;
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static constexpr OperationT Reset = 1 << 4;
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/// If set, indicates a read. Otherwise, a write.
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/// If set, indicates a read. Otherwise, a write.
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static constexpr int Read = 1 << 5;
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static constexpr OperationT Read = 1 << 5;
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/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
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/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
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static constexpr int IsData = 1 << 6;
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static constexpr OperationT IsData = 1 << 6;
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/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
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/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
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static constexpr int IsProgram = 1 << 7;
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static constexpr OperationT IsProgram = 1 << 7;
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/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
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/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
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/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
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/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
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static constexpr int InterruptAcknowledge = 1 << 8;
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static constexpr OperationT InterruptAcknowledge = 1 << 8;
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/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
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/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
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/// is synchronised with the E clock to satisfy a valid peripheral address request.
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/// is synchronised with the E clock to satisfy a valid peripheral address request.
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static constexpr int IsPeripheral = 1 << 9;
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static constexpr OperationT IsPeripheral = 1 << 9;
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/// Provides the 68000's bus grant line — indicating whether a bus request has been acknowledged.
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/// Provides the 68000's bus grant line — indicating whether a bus request has been acknowledged.
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static constexpr int BusGrant = 1 << 10;
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static constexpr OperationT BusGrant = 1 << 10;
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/// Contains a valid combination of the various static constexpr int flags, describing the operation
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/// Contains a valid combination of the various static constexpr int flags, describing the operation
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/// performed by this Microcycle.
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/// performed by this Microcycle.
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unsigned int operation = 0;
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OperationT operation = 0;
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/// Describes the duration of this Microcycle.
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/// Describes the duration of this Microcycle.
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HalfCycles length = HalfCycles(4);
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HalfCycles length = HalfCycles(4);
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@ -289,8 +291,8 @@ struct Microcycle {
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return ((*address) & 0x00fffffe) >> 1;
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return ((*address) & 0x00fffffe) >> 1;
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}
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}
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static constexpr int PermitRead = (1 << 11);
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static constexpr OperationT PermitRead = (1 << 11);
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static constexpr int PermitWrite = (1 << 12);
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static constexpr OperationT PermitWrite = (1 << 12);
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/*!
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/*!
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Assuming this to be a cycle with a data select active, applies it to @c target
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Assuming this to be a cycle with a data select active, applies it to @c target
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@ -300,21 +302,25 @@ struct Microcycle {
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* if this is a word read, reads a word (in the host platform's endianness) from @c target; and
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* if this is a word read, reads a word (in the host platform's endianness) from @c target; and
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* if this is a write, does the converse of a read.
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* if this is a write, does the converse of a read.
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*/
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*/
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forceinline void apply(uint8_t *target, int read_write_mask = PermitRead | PermitWrite) const {
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forceinline void apply(uint8_t *target, OperationT read_write_mask = PermitRead | PermitWrite) const {
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switch((operation | read_write_mask) & (SelectWord | SelectByte | Read | PermitRead | PermitWrite)) {
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switch((operation | read_write_mask) & (SelectWord | SelectByte | Read | PermitRead | PermitWrite)) {
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default:
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default:
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break;
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break;
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case SelectWord | Read | PermitRead:
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case SelectWord | Read | PermitRead:
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case SelectWord | Read | PermitRead | PermitWrite:
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value->full = *reinterpret_cast<uint16_t *>(target);
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value->full = *reinterpret_cast<uint16_t *>(target);
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break;
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break;
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case SelectByte | Read | PermitRead:
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case SelectByte | Read | PermitRead:
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case SelectByte | Read | PermitRead | PermitWrite:
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value->halves.low = *target;
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value->halves.low = *target;
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break;
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break;
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case SelectWord | PermitWrite:
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case SelectWord | PermitWrite:
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case SelectWord | PermitWrite | PermitRead:
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*reinterpret_cast<uint16_t *>(target) = value->full;
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*reinterpret_cast<uint16_t *>(target) = value->full;
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break;
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break;
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case SelectByte | PermitWrite:
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case SelectByte | PermitWrite:
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case SelectByte | PermitWrite | PermitRead:
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*target = value->halves.low;
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*target = value->halves.low;
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break;
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break;
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}
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}
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