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Add notes on R15.
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@ -110,7 +110,40 @@ struct Scheduler {
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}
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template <Flags f> void perform(DataProcessing fields) {
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// TODO: how does register 15 fit into all of below? As an operand or as a target?
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// TODO: ensure R15 is handled correctly.
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//
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// From the data sheet:
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//
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// # Writing to R15
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//
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// When Rd is a register other than R15, the condition code flags in the PSR may be
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// updated from the ALU flags as described above. When Rd is R15 and the S flag in
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// the instruction is set, the PSR is overwritten by the corresponding ALU result
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// ... in user mode the other flags (I, F, M1, M0) are protected from direct change
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// but in non-user modes these will also be affected, accepting copies of bits 27, 26,
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// 1 and 0 of the result respectively.
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//
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// ...
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//
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// If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written.
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// Conversely, if the instruction is of a type which does not normally produce a result
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// (CMP, CMN, TST, TEQ) but Rd is R15 and the S bit is set, the result will be used in
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// this case to update those PSR flags which are not protected by virtue of the
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// processor mode.
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//
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// # Using R15 as an operand
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//
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// When R15 appears in the Rm position it will give the value of the PC together
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// with the PSR flags to the barrel shifter.
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//
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// When R15 appears in either of the Rn or Rs positions it will give the value
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// of the PC alone, with the PSR bits replaced by zeroes.
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//
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// The PC value will be the address of the instruction, plus 8 or 12 bytes due to
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// instruction prefetching. If the shift amount is specified in the instruction, the
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// PC will be 8 bytes ahead. If a register is used to specify the shift amount, the
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// PC will be 8 bytes ahead when used as Rs and 12 bytes ahead when used as Rn
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// or Rm.
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constexpr DataProcessingFlags flags(f);
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auto &destination = registers_[fields.destination()];
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