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Corrects a few MOVE #s.

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This commit is contained in:
Thomas Harte 2019-04-17 10:00:14 -04:00
parent 82b08d0e3a
commit b64da2710a
2 changed files with 10 additions and 4 deletions
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7
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -79,12 +79,12 @@ class QL: public CPU::MC68000::BusHandler {
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %08x <- %04x] ", *cycle.address, cycle.value->full);
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %08x <- %02x] ", *cycle.address, (cycle.value->full >> cycle.byte_shift()) & 0xff);
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", (cycle.value->full >> cycle.byte_shift()) & 0xff, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->full & cycle.byte_mask()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}
@ -115,7 +115,8 @@ class QL: public CPU::MC68000::BusHandler {
- (void)testStartup {
// This is an example of a functional test case.
// Use XCTAssert and related functions to verify your tests produce the correct results.
_machine->run_for(HalfCycles(16000000));
_machine->run_for(HalfCycles(40000000));
}
@end

7
Processors/68000/Implementation/68000Storage.cpp
View File

@ -2413,7 +2413,8 @@ struct ProcessorStorageConstructor {
case bw2(Imm, d8AnXn): // MOVE.bw #, (d8, An, Xn)
case bw2(Imm, d16PC): // MOVE.bw #, (d16, PC)
case bw2(Imm, d8PCXn): // MOVE.bw #, (d8, PC, Xn)
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq(pseq("np nw np", destination_mode), { ea(1) }, !is_byte_access ));
op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsl);
break;
@ -2546,18 +2547,21 @@ struct ProcessorStorageConstructor {
break;
case bw2(Imm, XXXw): // MOVE.bw #, (xxx).w
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
break;
case bw2(Imm, XXXl): // MOVE.bw #, (xxx).l
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }));
op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
break;
case l2(Imm, XXXw): // MOVE.l #, (xxx).w
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::None), seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
@ -2565,6 +2569,7 @@ struct ProcessorStorageConstructor {
break;
case l2(Imm, XXXl): // MOVE.l #, (xxx).l
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
op(int(Action::None), seq("np"));
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));