From b67331e01899f4d6deee9f125376756d9b67c8d2 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 29 May 2017 10:48:53 -0400 Subject: [PATCH] Fixing the OUT repetition group reduces the code to one failing test. --- OSBindings/Mac/Clock SignalTests/FUSETests.swift | 4 ++-- Processors/Z80/Z80.hpp | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/OSBindings/Mac/Clock SignalTests/FUSETests.swift b/OSBindings/Mac/Clock SignalTests/FUSETests.swift index 014ba73ae..269b2c167 100644 --- a/OSBindings/Mac/Clock SignalTests/FUSETests.swift +++ b/OSBindings/Mac/Clock SignalTests/FUSETests.swift @@ -167,7 +167,7 @@ class FUSETests: XCTestCase { let name = itemDictionary["name"] as! String -// if name != "eda2" { +// if name != "eda3" { // continue; // } @@ -194,7 +194,7 @@ class FUSETests: XCTestCase { let finalState = RegisterState(machine: machine) - XCTAssert(finalState == targetState, "Failed \(name)") + XCTAssertEqual(finalState, targetState, "Failed \(name)") // if finalState != targetState { // failures = failures + 1 // if failures == 5 { diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp index 770300532..167441d27 100644 --- a/Processors/Z80/Z80.hpp +++ b/Processors/Z80/Z80.hpp @@ -390,22 +390,22 @@ template class Processor: public MicroOpScheduler { /* 0xa0 LDI */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDI}), /* 0xa1 CPI */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPI}), /* 0xa2 INI */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INI}), - /* 0xa3 OTI */ Program(OUT(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTI}), + /* 0xa3 OTI */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTI}), XX, XX, XX, XX, /* 0xa8 LDD */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDD}), /* 0xa9 CPD */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPD}), /* 0xaa IND */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::IND}), - /* 0xab OTD */ Program(OUT(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTD}), + /* 0xab OTD */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTD}), XX, XX, XX, XX, /* 0xb0 LDIR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDIR}, WAIT(5)), /* 0xb1 CPIR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPIR}, WAIT(5)), /* 0xb2 INIR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INIR}, WAIT(5)), - /* 0xb3 OTIR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTIR}, WAIT(5)), + /* 0xb3 OTIR */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTIR}, WAIT(5)), XX, XX, XX, XX, /* 0xb8 LDDR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDDR}, WAIT(5)), /* 0xb9 CPDR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPDR}, WAIT(5)), /* 0xba INDR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INDR}, WAIT(5)), - /* 0xbb OTDR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTDR}, WAIT(5)), + /* 0xbb OTDR */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTDR}, WAIT(5)), XX, XX, XX, XX, NOP_ROW(), /* 0xc0 */ NOP_ROW(), /* 0xd0 */