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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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@ -718,4 +718,50 @@ class Z80MachineCycleTests: XCTestCase {
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]
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)
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}
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func testRLCA() {
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test(
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program: [0x07],
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busCycles: [
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MachineCycle(operation: .readOpcode, length: 4),
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]
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)
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}
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func testRLCr() {
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test(
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program: [0xcb, 0x00],
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busCycles: [
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MachineCycle(operation: .readOpcode, length: 4),
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MachineCycle(operation: .readOpcode, length: 4),
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]
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)
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}
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func testRLCHL() {
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test(
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program: [0xcb, 0x06],
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busCycles: [
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MachineCycle(operation: .readOpcode, length: 4),
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MachineCycle(operation: .readOpcode, length: 4),
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MachineCycle(operation: .read, length: 4),
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MachineCycle(operation: .write, length: 3),
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]
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)
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}
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// RLC (IX+d) (NB: the official table doesn't read the final part of the instruction; I've assumed a five-cycle version of read opcode replaces the internal operation)
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func testRLCIX() {
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test(
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program: [0xdd, 0xcb, 0x00, 0x06],
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busCycles: [
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MachineCycle(operation: .readOpcode, length: 4),
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MachineCycle(operation: .readOpcode, length: 4),
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MachineCycle(operation: .read, length: 3),
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MachineCycle(operation: .readOpcode, length: 5),
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MachineCycle(operation: .read, length: 4),
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MachineCycle(operation: .write, length: 3),
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]
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)
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}
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}
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@ -338,7 +338,7 @@ template <class T> class Processor {
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StdInstr({MicroOp::op, &a_})
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#define RMW(x, op, ...) StdInstr(INDEX(), Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
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#define RMWI(x, op, ...) Instr(4, Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
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#define RMWI(x, op, ...) Instr(3, Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
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#define MODIFY_OP_GROUP(op) \
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StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \
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