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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.

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This commit is contained in:
Thomas Harte 2017-06-19 20:33:34 -04:00
parent 351d90ca55
commit b684254908
2 changed files with 47 additions and 1 deletions
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46
OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift
View File

@ -718,4 +718,50 @@ class Z80MachineCycleTests: XCTestCase {
]
)
}
func testRLCA() {
test(
program: [0x07],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
]
)
}
func testRLCr() {
test(
program: [0xcb, 0x00],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
]
)
}
func testRLCHL() {
test(
program: [0xcb, 0x06],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 4),
MachineCycle(operation: .write, length: 3),
]
)
}
// RLC (IX+d) (NB: the official table doesn't read the final part of the instruction; I've assumed a five-cycle version of read opcode replaces the internal operation)
func testRLCIX() {
test(
program: [0xdd, 0xcb, 0x00, 0x06],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .readOpcode, length: 5),
MachineCycle(operation: .read, length: 4),
MachineCycle(operation: .write, length: 3),
]
)
}
}

2
Processors/Z80/Z80.hpp
View File

@ -338,7 +338,7 @@ template <class T> class Processor {
StdInstr({MicroOp::op, &a_})
#define RMW(x, op, ...) StdInstr(INDEX(), Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
#define RMWI(x, op, ...) Instr(4, Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
#define RMWI(x, op, ...) Instr(3, Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
#define MODIFY_OP_GROUP(op) \
StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \