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Ensures the value initially loaded to A7 is aligned.
This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
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@ -191,6 +191,11 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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case BusStep::Action::DecrementEffectiveAddress1: effective_address_[1].full -= 2; break;
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case BusStep::Action::DecrementEffectiveAddress1: effective_address_[1].full -= 2; break;
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case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break;
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case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break;
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case BusStep::Action::IncrementEffectiveAddress0AlignStackPointer:
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effective_address_[0].full += 2;
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address_[7].full &= 0xffff'fffe;
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break;
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case BusStep::Action::AdvancePrefetch:
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case BusStep::Action::AdvancePrefetch:
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prefetch_queue_.halves.high = prefetch_queue_.halves.low;
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prefetch_queue_.halves.high = prefetch_queue_.halves.low;
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@ -299,6 +304,14 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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}
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}
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#endif
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#endif
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static uint32_t last_a7 = address_[7].full;
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log |= (program_counter_.full - 4 == 0x00fcafba);
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// if(log) {
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if(log && last_a7 != address_[7].full) {
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last_a7 = address_[7].full;
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printf("%08x a7:%08x\n", program_counter_.full - 4, address_[7].full);
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}
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decoded_instruction_.full = prefetch_queue_.halves.high.full;
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decoded_instruction_.full = prefetch_queue_.halves.high.full;
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#ifndef NDEBUG
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#ifndef NDEBUG
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@ -261,7 +261,7 @@ struct ProcessorStorageConstructor {
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steps.push_back(step);
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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step.action = isupper(access_pattern[1]) ? Action::IncrementEffectiveAddress0 : Action::IncrementEffectiveAddress0AlignStackPointer;
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steps.push_back(step);
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steps.push_back(step);
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continue;
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continue;
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@ -196,6 +196,9 @@ class ProcessorStorage {
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/// Copies prefetch_queue_[1] to prefetch_queue_[0].
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/// Copies prefetch_queue_[1] to prefetch_queue_[0].
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AdvancePrefetch,
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AdvancePrefetch,
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/// Performs effective_address_[0] += 2 and zeroes the final bit of the stack pointer.
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IncrementEffectiveAddress0AlignStackPointer,
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/*!
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/*!
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Terminates an atomic program; if nothing else is pending, schedules the next instruction.
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Terminates an atomic program; if nothing else is pending, schedules the next instruction.
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This action is special in that it usurps any included microcycle. So any Step with this
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This action is special in that it usurps any included microcycle. So any Step with this
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@ -550,6 +553,8 @@ class ProcessorStorage {
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inline uint16_t get_status() const;
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inline uint16_t get_status() const;
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inline void set_status(uint16_t);
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inline void set_status(uint16_t);
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bool log = false;
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private:
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private:
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friend struct ProcessorStorageConstructor;
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friend struct ProcessorStorageConstructor;
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friend class ProcessorStorageTests;
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friend class ProcessorStorageTests;
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