From b84fa619dac6a3c13de0d3f6b7d8972ae33a426f Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sat, 2 Apr 2022 15:27:12 -0400 Subject: [PATCH] Test integer loads and stores. --- InstructionSets/PowerPC/Instruction.hpp | 81 +++++++++++++++++-- .../DingusdevPowerPCTests.mm | 46 +++++++++++ 2 files changed, 120 insertions(+), 7 deletions(-) diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp index 29b680f22..10b05b87c 100644 --- a/InstructionSets/PowerPC/Instruction.hpp +++ b/InstructionSets/PowerPC/Instruction.hpp @@ -331,18 +331,40 @@ enum class Operation: uint8_t { fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx, fdivx, fdivsx, fmaddx, fmaddsx, fmrx, fmsubx, fmsubsx, fmulx, fmulsx, fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx, - icbi, isync, lbz, lbzu, + icbi, isync, + + /// Load byte and zero. + /// lbz + /// rD(), d() [ rA() ] + lbz, + + /// Load byte and zero with update. + /// lbz + /// rD(), d() [ rA() ] + lbzu, /// Load byte and zero with update indexed. /// lbzux + /// rD(), rA(), rB() lbzux, /// Load byte and zero indexed. /// lbzx + /// rD(), rA(), rB() lbzx, lfd, lfdu, lfdux, lfdx, lfs, lfsu, - lfsux, lfsx, lha, lhau, + lfsux, lfsx, + + /// Load half word algebraic. + /// lha + /// rD(), d() [ rA() ] + lha, + + /// Load half word algebraic with update. + /// lha + /// rD(), d() [ rA() ] + lhau, /// Load half-word algebraic with update indexed. /// lhaux @@ -361,12 +383,12 @@ enum class Operation: uint8_t { /// Load half word and zero. /// lhz - /// rD(), d()[ rA() ] + /// rD(), d() [ rA() ] lhz, /// Load half-word and zero with update. /// lhzu - /// rD(), d()[ rA() ] + /// rD(), d() [ rA() ] lhzu, /// Load half-word and zero with update indexed. @@ -533,19 +555,64 @@ enum class Operation: uint8_t { stfs, /// Store floating point single precision with update. - /// stfs + /// stfsu /// frS() d() [ rA() ] stfsu, - stfsux, stfsx, sth, sthbrx, sthu, + /// Store floating point single precision with update indexed. + /// stfsux + /// frS(), rA(), rB() + stfsux, + + /// Store floating point single precisionindexed. + /// stfsx + /// frS(), rA(), rB() + stfsx, + + /// Store half word. + /// sth + /// rS(), d() [ rA() ] + sth, + + /// Store half word byte-reverse indexed. + /// sthbrx + /// rS(), rA(), rB() + sthbrx, + + /// Store half word with update. + /// sthu + /// rS(), d() [ rA() ] + sthu, /// Store half-word with update indexed. + /// sthux + /// rS(), rA(), rB() sthux, /// Store half-word indexed. + /// sthx + /// rS(), rA(), rB() sthx, - stmw, stswi, stswx, stw, + /// Store multiple word. + /// stmw + /// rS(), d() [ rA() ] + stmw, + + /// Store string word immediate. + /// stswi + /// rS(), rA(), nb() + stswi, + + /// Store string word indexed. + /// stswx + /// rS(), rA(), rB() + stswx, + + /// Store word. + /// stw + /// rS(), d() [ rA() ] + stw, /// Store word byte-reverse indexed. /// stwbrx diff --git a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm index 265a7fdba..a3b90e7c8 100644 --- a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm +++ b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm @@ -92,6 +92,16 @@ NSString *condition(uint32_t code) { } } +NSString *offset(Instruction instruction) { + NSString *const hexPart = [NSString stringWithFormat:@"%s%X", (instruction.d() < 0) ? "-0x" : "0x", abs(instruction.d())]; + + if(instruction.rA()) { + return [hexPart stringByAppendingFormat:@"(r%d)", instruction.rA()]; + } else { + return hexPart; + } +} + } @implementation DingusdevPowerPCTests @@ -464,6 +474,42 @@ NSString *condition(uint32_t code) { #undef SAB +#define DDA(x) \ + case Operation::x: { \ + AssertEqualOperationName(operation, @#x, instruction); \ + AssertEqualR(columns[3], instruction.rD()); \ + XCTAssertEqualObjects(columns[4], offset(instruction)); \ + } break; + + DDA(lbz); + DDA(lbzu); + DDA(lmw); + DDA(lwz); + DDA(lwzu); + DDA(lhz); + DDA(lhzu); + DDA(lha); + DDA(lhau); + +#undef DDA + +#define SDA(x) \ + case Operation::x: { \ + AssertEqualOperationName(operation, @#x, instruction); \ + AssertEqualR(columns[3], instruction.rS()); \ + XCTAssertEqualObjects(columns[4], offset(instruction)); \ + } break; + + SDA(stb); + SDA(stbu); + SDA(sth); + SDA(sthu); + SDA(stmw); + SDA(stw); + SDA(stwu); + +#undef SDA + case Operation::bcx: case Operation::bclrx: case Operation::bcctrx: {