From b8848d8580ec04f291e92e3548b835764ca84d2e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sat, 10 Oct 2020 21:43:05 -0400 Subject: [PATCH] Implements TCD, TDC, TCS, TSC. --- .../Implementation/65816Implementation.hpp | 33 ++++++++++++++----- .../65816/Implementation/65816Storage.cpp | 2 ++ 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp index 34b8dca01..9a8ab646d 100644 --- a/Processors/65816/Implementation/65816Implementation.hpp +++ b/Processors/65816/Implementation/65816Implementation.hpp @@ -26,6 +26,7 @@ template void Processor::run_for(const Cycles #define x() (x_.full & x_masks_[1]) #define y() (y_.full & x_masks_[1]) +#define stack_address() ((s_.full & e_masks_[1]) | (0x0100 & e_masks_[0])) Cycles number_of_cycles = cycles + cycles_left_to_run_; while(number_of_cycles > Cycles(0)) { @@ -143,11 +144,7 @@ template void Processor::run_for(const Cycles // #define stack_access(value, operation) \ - if(emulation_flag_) { \ - bus_address = s_.halves.low | 0x100; \ - } else { \ - bus_address = s_.full; \ - } \ + bus_address = stack_address(); \ bus_value = value; \ bus_operation = operation; @@ -369,7 +366,7 @@ template void Processor::run_for(const Cycles switch(active_instruction_->operation) { // - // Loads, stores and transfers (and NOP). + // Loads, stores and transfers (and NOP, and XBA). // case LDA: @@ -450,7 +447,7 @@ template void Processor::run_for(const Cycles // The below attempt to obey the 8/16-bit mixed transfer rules // as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM - // (and makes reasonable guesses as to the N flag) + // (and make reasonable guesses as to the N flag). case TXS: s_ = x_.full & x_masks_[1]; @@ -491,6 +488,26 @@ template void Processor::run_for(const Cycles flags_.set_nz(a_.full, m_shift_); break; + case TCD: + direct_ = a_.full; + flags_.set_nz(a_.full, 8); + break; + + case TDC: + a_.full = direct_; + flags_.set_nz(a_.full, 8); + break; + + case TCS: + s_.full = a_.full; + // No need to worry about byte masking here; for the stack it's handled as the emulation runs. + break; + + case TSC: + a_.full = stack_address(); + flags_.set_nz(a_.full, 8); + break; + case XBA: { const uint8_t a_low = a_.halves.low; a_.halves.low = a_.halves.high; @@ -793,7 +810,6 @@ template void Processor::run_for(const Cycles // TRB, TSB, // STP, WAI, // RTL, - // TCD, TCS, TDC, TSC default: assert(false); @@ -820,6 +836,7 @@ template void Processor::run_for(const Cycles #undef y #undef m_flag #undef x_flag +#undef stack_address cycles_left_to_run_ = number_of_cycles; } diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp index 472616e2e..d4943da02 100644 --- a/Processors/65816/Implementation/65816Storage.cpp +++ b/Processors/65816/Implementation/65816Storage.cpp @@ -1046,6 +1046,8 @@ void ProcessorStorage::set_emulation_mode(bool enabled) { } else { e_masks_[0] = 0x0000; e_masks_[1] = 0xffff; + s_.halves.high = 1; // To pretend it was 1 all along; this implementation actually ignores + // the top byte while in emulation mode. } emulation_flag_ = enabled;