From 463fbb07f9e8f859552a75d403f8c98271fadfe1 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 10:55:03 -0400
Subject: [PATCH 1/6] Adapt remaining 68000 tests to use Mk2.

---
 InstructionSets/M68k/RegisterSet.hpp          |   5 +
 InstructionSets/M68k/Status.hpp               |   2 +
 .../Clock SignalTests/68000ArithmeticTests.mm | 628 +++++++++---------
 .../Mac/Clock SignalTests/68000BCDTests.mm    | 150 ++---
 .../Clock SignalTests/68000BitwiseTests.mm    | 530 +++++++--------
 .../68000ControlFlowTests.mm                  | 156 ++---
 .../Mac/Clock SignalTests/68000MoveTests.mm   | 434 ++++++------
 .../Clock SignalTests/68000RollShiftTests.mm  | 494 +++++++-------
 .../Mac/Clock SignalTests/68000Tests.mm       |  28 +-
 .../Mac/Clock SignalTests/TestRunner68000.hpp |  31 +-
 10 files changed, 1234 insertions(+), 1224 deletions(-)

diff --git a/InstructionSets/M68k/RegisterSet.hpp b/InstructionSets/M68k/RegisterSet.hpp
index c10c97364..87e98f70b 100644
--- a/InstructionSets/M68k/RegisterSet.hpp
+++ b/InstructionSets/M68k/RegisterSet.hpp
@@ -18,6 +18,11 @@ struct RegisterSet {
 	uint32_t supervisor_stack_pointer;
 	uint16_t status;
 	uint32_t program_counter;
+
+	/// @returns The active stack pointer, whichever it may be.
+	uint32_t stack_pointer() const {
+		return (status & 0x2000) ? supervisor_stack_pointer : user_stack_pointer;
+	}
 };
 
 }
diff --git a/InstructionSets/M68k/Status.hpp b/InstructionSets/M68k/Status.hpp
index c0af4d9f8..d43a6dbd4 100644
--- a/InstructionSets/M68k/Status.hpp
+++ b/InstructionSets/M68k/Status.hpp
@@ -22,6 +22,8 @@ static constexpr uint16_t Zero			= 1 << 2;
 static constexpr uint16_t Negative		= 1 << 3;
 static constexpr uint16_t Extend		= 1 << 4;
 
+static constexpr uint16_t AllConditions	= Carry | Overflow | Zero | Negative | Extend;
+
 static constexpr uint16_t Supervisor	= 1 << 13;
 static constexpr uint16_t Trace			= 1 << 15;
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
index f0fb7aa49..625e94030 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
@@ -43,13 +43,13 @@
 		0x0602, 0xff		// ADD.B #$ff, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x9ae;
+	state.registers.data[2] = 0x9ae;
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x9ad);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x9ad);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -58,13 +58,13 @@
 		0xd43c, 0x82		// ADD.B #$82, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x82;
+	state.registers.data[2] = 0x82;
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x04);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x04);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -73,14 +73,14 @@
 		0xd538, 0x3000		// ADD.B D2, ($3000).W
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x82;
+	state.registers.data[2] = 0x82;
 	*self.machine->ram_at(0x3000) = 0x8200;
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x82);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x82);
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0400);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
@@ -90,12 +90,12 @@
 		0xd442		// ADD.W D2, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x3e8;
+	state.registers.data[2] = 0x3e8;
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x7D0);
+	XCTAssertEqual(state.registers.data[2], 0x7D0);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -104,8 +104,8 @@
 		0xd59a		// ADD.L D2, (A2)+
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xb2d05e00;
-	state.address[2] = 0x2000;
+	state.registers.data[2] = 0xb2d05e00;
+	state.registers.address[2] = 0x2000;
 	*self.machine->ram_at(0x2000) = 0x7735;
 	*self.machine->ram_at(0x2002) = 0x9400;
 
@@ -113,10 +113,10 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xb2d05e00);
+	XCTAssertEqual(state.registers.data[2], 0xb2d05e00);
 	XCTAssertEqual(*self.machine->ram_at(0x2000), 0x2a05);
 	XCTAssertEqual(*self.machine->ram_at(0x2002), 0xf200);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -125,8 +125,8 @@
 		0xd462		// ADD.W -(A2), D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xFFFF0000;
-	state.address[2] = 0x2002;
+	state.registers.data[2] = 0xFFFF0000;
+	state.registers.address[2] = 0x2002;
 	*self.machine->ram_at(0x2000) = 0;
 	*self.machine->ram_at(0x2002) = 0xffff;
 
@@ -134,9 +134,9 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xFFFF0000);
-	XCTAssertEqual(state.address[2], 0x2000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[2], 0xFFFF0000);
+	XCTAssertEqual(state.registers.address[2], 0x2000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(10, self.machine->get_cycle_count());
 }
 
@@ -150,16 +150,16 @@
 		0xd481		// ADD.l D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfe35aab0;
-	state.data[2] = 0x012557ac;
+	state.registers.data[1] = 0xfe35aab0;
+	state.registers.data[2] = 0x012557ac;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfe35aab0);
-	XCTAssertEqual(state.data[2], 0xff5b025c);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xfe35aab0);
+	XCTAssertEqual(state.registers.data[2], 0xff5b025c);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -176,15 +176,15 @@
 		0xd5fc, 0x1234, 0x5678		// ADDA.L #$12345678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
+	state.registers.address[2] = 0xae43ab1d;
+	state.registers.status = ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xc0780195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0xc0780195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWPositive {
@@ -192,15 +192,15 @@
 		0xd4fc, 0x5678		// ADDA.W #$5678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
+	state.registers.address[2] = 0xae43ab1d;
+	state.registers.status = ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xae440195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0xae440195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWNegative {
@@ -208,15 +208,15 @@
 		0xd4fc, 0xf678		// ADDA.W #$f678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
+	state.registers.address[2] = 0xae43ab1d;
+	state.registers.status = ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xae43a195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0xae43a195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWNegative_2 {
@@ -224,14 +224,14 @@
 		0xd4fc, 0xf000		// ADDA.W #$f000, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.status = Flag::ConditionCodes;
+	state.registers.status = ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xfffff000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0xfffff000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDALPreDec {
@@ -239,8 +239,8 @@
 		0xd5e2				// ADDA.L -(A2), A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.status = Flag::ConditionCodes;
-	state.address[2] = 0x2004;
+	state.registers.status = ConditionCode::AllConditions;
+	state.registers.address[2] = 0x2004;
 	*self.machine->ram_at(0x2000) = 0x7002;
 	*self.machine->ram_at(0x2002) = 0;
 
@@ -248,10 +248,10 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x70022000);
+	XCTAssertEqual(state.registers.address[2], 0x70022000);
 	XCTAssertEqual(*self.machine->ram_at(0x2000), 0x7002);
 	XCTAssertEqual(*self.machine->ram_at(0x2002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 @end
@@ -267,17 +267,17 @@
 		0xd581		// ADDX.l D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12345678;
-	state.data[2] = 0x12345678;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = 0x12345678;
+	state.registers.data[2] = 0x12345678;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x2468acf1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x2468acf1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -286,16 +286,16 @@
 		0xd501		// ADDX.b D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x80;
-	state.data[2] = 0x8080;
+	state.registers.data[1] = 0x80;
+	state.registers.data[2] = 0x8080;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x80);
-	XCTAssertEqual(state.data[2], 0x8000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Overflow | Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x80);
+	XCTAssertEqual(state.registers.data[2], 0x8000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -304,17 +304,17 @@
 		0xd541		// ADDX.w D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x1ffff;
-	state.data[2] = 0x18080;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = 0x1ffff;
+	state.registers.data[2] = 0x18080;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1ffff);
-	XCTAssertEqual(state.data[2], 0x18080);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x1ffff);
+	XCTAssertEqual(state.registers.data[2], 0x18080);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -323,8 +323,8 @@
 		0xd389		// ADDX.l -(A1), -(A1)
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.status |= Flag::ConditionCodes;
+	state.registers.address[1] = 0x3000;
+	state.registers.status |= ConditionCode::AllConditions;
 	*self.machine->ram_at(0x2ff8) = 0x1000;
 	*self.machine->ram_at(0x2ffa) = 0x0000;
 	*self.machine->ram_at(0x2ffc) = 0x7000;
@@ -334,8 +334,8 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(*self.machine->ram_at(0x2ff8), 0x8000);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffa), 0x1ff2);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffc), 0x7000);
@@ -356,14 +356,14 @@
 		0x0681, 0x1111, 0x1111		// ADDI.l #$11111111, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x300021b3;
+	state.registers.data[1] = 0x300021b3;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x411132C4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x411132C4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
 
@@ -377,7 +377,7 @@
 
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x2554);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -394,14 +394,14 @@
 		0x5e81		// ADDQ.l #$7, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xffffffff;
+	state.registers.data[1] = 0xffffffff;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x6);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x6);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -410,14 +410,14 @@
 		0x5641		// ADDQ.W #$3, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfffffffe;
+	state.registers.data[1] = 0xfffffffe;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffff0001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xffff0001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -426,14 +426,14 @@
 		0x5649		// ADDQ.W #$3, A1
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0xfffffffe;
+	state.registers.address[1] = 0xfffffffe;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[1], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -447,7 +447,7 @@
 
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x8005);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
 
@@ -464,25 +464,25 @@
 		opcode
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x1234567f;
-	state.data[2] = 0x12345680;
+	state.registers.data[1] = 0x1234567f;
+	state.registers.data[2] = 0x12345680;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234567f);
-	XCTAssertEqual(state.data[2], 0x12345680);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
+	XCTAssertEqual(state.registers.data[1], 0x1234567f);
+	XCTAssertEqual(state.registers.data[2], 0x12345680);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, flags);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
 - (void)testCMPb_D1D2 {
-	[self performCMPb:0xb401 expectedFlags:Flag::Overflow];	// CMP.b D1, D2
+	[self performCMPb:0xb401 expectedFlags:ConditionCode::Overflow];	// CMP.b D1, D2
 }
 
 - (void)testCMPb_D2D1 {
-	[self performCMPb:0xb202 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry];	// CMP.b D2, D1
+	[self performCMPb:0xb202 expectedFlags:ConditionCode::Overflow | ConditionCode::Negative | ConditionCode::Carry];	// CMP.b D2, D1
 }
 
 - (void)performCMPwd1:(uint32_t)d1 d2:(uint32_t)d2 expectedFlags:(uint16_t)flags {
@@ -490,25 +490,25 @@
 		0xb242		// CMP.W D2, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
+	state.registers.data[1] = d1;
+	state.registers.data[2] = d2;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.data[2], d2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.data[2], d2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, flags);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
 - (void)testCMPw_8004v7002 {
-	[self performCMPwd1:0x12347002 d2:0x12348004 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry];
+	[self performCMPwd1:0x12347002 d2:0x12348004 expectedFlags:ConditionCode::Overflow | ConditionCode::Negative | ConditionCode::Carry];
 }
 
 - (void)testCMPw_6666v5555 {
-	[self performCMPwd1:0x55555555 d2:0x66666666 expectedFlags:Flag::Negative | Flag::Carry];
+	[self performCMPwd1:0x55555555 d2:0x66666666 expectedFlags:ConditionCode::Negative | ConditionCode::Carry];
 }
 
 - (void)testCMPl {
@@ -516,16 +516,16 @@
 		0xb282		// CMP.l D2, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12347002;
-	state.data[2] = 0x12348004;
+	state.registers.data[1] = 0x12347002;
+	state.registers.data[2] = 0x12348004;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12347002);
-	XCTAssertEqual(state.data[2], 0x12348004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x12347002);
+	XCTAssertEqual(state.registers.data[2], 0x12348004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -542,15 +542,15 @@
 		0xb5c1		// CMPA.l D1, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.address[2] = a2;
+	state.registers.data[1] = d1;
+	state.registers.address[2] = a2;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[2], a2);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[2], a2);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -558,21 +558,21 @@
 	[self performCMPAld1:0x1234567f a2:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testCMPAl_carry {
 	[self performCMPAld1:0xfd234577 a2:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 }
 
 - (void)testCMPAl_carryOverflowNegative {
 	[self performCMPAld1:0x85678943 a2:0x22563245];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Overflow | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Negative);
 }
 
 - (void)performCMPAwd1:(uint32_t)d1 a2:(uint32_t)a2 {
@@ -580,15 +580,15 @@
 		0xb4c1		// CMPA.w D1, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.address[2] = a2;
+	state.registers.data[1] = d1;
+	state.registers.address[2] = a2;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[2], a2);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[2], a2);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -596,14 +596,14 @@
 	[self performCMPAwd1:0x85678943 a2:0x22563245];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 }
 
 - (void)testCMPAw_zero {
 	[self performCMPAwd1:0x0000ffff a2:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 @end
@@ -619,14 +619,14 @@
 		0x0c41, 0xffff		// CMPI.W #$ffff, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfff2ffff;
+	state.registers.data[1] = 0xfff2ffff;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfff2ffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0xfff2ffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -635,14 +635,14 @@
 		0x0c81, 0x8000, 0x0000		// CMPI.L #$80000000, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x7fffffff;
+	state.registers.data[1] = 0x7fffffff;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x7fffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x7fffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -651,14 +651,14 @@
 		0x0c01, 0x0090		// CMPI.B #$90, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x8f;
+	state.registers.data[1] = 0x8f;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x8f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x8f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -675,8 +675,8 @@
 		0xb389		// CMPM.L (A1)+, (A1)+
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.status |= Flag::ConditionCodes;
+	state.registers.address[1] = 0x3000;
+	state.registers.status |= ConditionCode::AllConditions;
 	*self.machine->ram_at(0x3000) = 0x7000;
 	*self.machine->ram_at(0x3002) = 0x1ff1;
 	*self.machine->ram_at(0x3004) = 0x1000;
@@ -686,8 +686,8 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3008);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.address[1], 0x3008);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -696,9 +696,9 @@
 		0xb549		// CMPM.w (A1)+, (A2)+
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.address[2] = 0x3002;
-	state.status |= Flag::ConditionCodes;
+	state.registers.address[1] = 0x3000;
+	state.registers.address[2] = 0x3002;
+	state.registers.status |= ConditionCode::AllConditions;
 	*self.machine->ram_at(0x3000) = 0;
 	*self.machine->ram_at(0x3002) = 0;
 
@@ -706,9 +706,9 @@
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3002);
-	XCTAssertEqual(state.address[2], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero | Flag::Extend);
+	XCTAssertEqual(state.registers.address[1], 0x3002);
+	XCTAssertEqual(state.registers.address[2], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero | ConditionCode::Extend);
 	XCTAssertEqual(12, self.machine->get_cycle_count());
 }
 
@@ -717,18 +717,18 @@
 		0xb509		// CMPM.b (A1)+, (A2)+
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.address[2] = 0x3001;
-	state.status |= Flag::ConditionCodes;
+	state.registers.address[1] = 0x3000;
+	state.registers.address[2] = 0x3001;
+	state.registers.status |= ConditionCode::AllConditions;
 	*self.machine->ram_at(0x3000) = 0x807f;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3001);
-	XCTAssertEqual(state.address[2], 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.address[1], 0x3001);
+	XCTAssertEqual(state.registers.address[2], 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 	XCTAssertEqual(12, self.machine->get_cycle_count());
 }
 
@@ -745,8 +745,8 @@
 		0x83fc, divisor		// DIVS #divisor, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = d1;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -756,8 +756,8 @@
 	[self performDIVS:divisor d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -777,8 +777,8 @@
 	[self performDIVS:0xeef0 d1:0x0768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x026190D3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x026190D3);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(138, self.machine->get_cycle_count());
 }
 
@@ -786,8 +786,8 @@
 	[self performDIVS:0xffff d1:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -795,8 +795,8 @@
 	[self performDIVS:0x3333 d1:0xffff0000];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfffffffb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xfffffffb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -804,8 +804,8 @@
 	[self performDIVS:0x23 d1:0x8765];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xb03de);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0xb03de);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(138, self.machine->get_cycle_count());
 }
 
@@ -813,8 +813,8 @@
 	[self performDIVS:0x8765 d1:0x65];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x650000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x650000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(156, self.machine->get_cycle_count());
 }
 
@@ -823,8 +823,8 @@
 	[self performDIVS:0xffff d1:0x80000000];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x80000000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x80000000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -833,8 +833,8 @@
 	[self performDIVS:0xfffd d1:0xfffffffd];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -843,8 +843,8 @@
 	[self performDIVS:0x7aee d1:0xdaaa00fe];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xc97eb240);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xc97eb240);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(148, self.machine->get_cycle_count());
 }
 
@@ -853,8 +853,8 @@
 	[self performDIVS:0x7fff d1:0x82f9fff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x305e105f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x305e105f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(142, self.machine->get_cycle_count());
 }
 
@@ -863,8 +863,8 @@
 	[self performDIVS:0xf32 d1:0x00e1d44];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x0bfa00ed);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x0bfa00ed);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(144, self.machine->get_cycle_count());
 }
 
@@ -873,8 +873,8 @@
 	[self performDIVS:0xaf32 d1:0xe1d44];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x39dcffd4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x39dcffd4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(150, self.machine->get_cycle_count());
 }
 
@@ -884,11 +884,11 @@
 	self.machine->set_initial_stack_pointer(initial_sp);
 	[self performDIVS:0x0 d1:0x1fffffff];
 
-	// Check register state.
+	// Check register state.registers.
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1fffffff);
-	XCTAssertEqual(state.supervisor_stack_pointer, initial_sp - 6);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x1fffffff);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, initial_sp - 6);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(42, self.machine->get_cycle_count());
 
 	// Check stack contents; should be PC.l, PC.h and status register.
@@ -916,8 +916,8 @@
 		0x82fc, divisor		// DIVU #$eef0, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = d1;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -927,8 +927,8 @@
 	[self performDIVU:1 d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -936,8 +936,8 @@
 	[self performDIVU:0x1234 d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -945,8 +945,8 @@
 	[self performDIVU:0xeeff d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x8bae4c7d);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x8bae4c7d);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(108, self.machine->get_cycle_count());
 }
 
@@ -954,8 +954,8 @@
 	[self performDIVU:0x3333 d1:0x1fffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1fffa000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x1fffa000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(136, self.machine->get_cycle_count());
 }
 
@@ -975,8 +975,8 @@
 	});
 
 	auto state = self.machine->get_processor_state();
-	state.data[3] = d3;
-	state.status = 0x13;
+	state.registers.data[3] = d3;
+	state.registers.status = 0x13;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -988,24 +988,24 @@
 	[self performEXTwd3:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x12340078);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[3], 0x12340078);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testEXTw_00 {
 	[self performEXTwd3:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x12340000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x12340000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 }
 
 - (void)testEXTw_f0 {
 	[self performEXTwd3:0x123456f0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x1234fff0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[3], 0x1234fff0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testEXTl {
@@ -1014,8 +1014,8 @@
 	});
 
 	auto state = self.machine->get_processor_state();
-	state.data[3] = 0x1234f6f0;
-	state.status = 0x13;
+	state.registers.data[3] = 0x1234f6f0;
+	state.registers.status = 0x13;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1023,8 +1023,8 @@
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0xfffff6f0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[3], 0xfffff6f0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 }
 
 @end
@@ -1040,9 +1040,9 @@
 		0xc5c1		// MULS D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status = ccr;
+	state.registers.data[1] = d1;
+	state.registers.data[2] = d2;
+	state.registers.status = ccr;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1053,8 +1053,8 @@
 		0xc5fc, constant		// MULS #constant, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = d2;
-	state.status = Flag::Carry | Flag::Extend | Flag::Overflow;
+	state.registers.data[2] = d2;
+	state.registers.status = ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Overflow;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1064,9 +1064,9 @@
 	[self performMULSd1:0x12345678 d2:0x12345678 ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x1d34d840);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x1d34d840);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(54, self.machine->get_cycle_count());
 }
 
@@ -1074,19 +1074,19 @@
 	[self performMULSd1:0x82348678 d2:0x823486ff ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x82348678);
-	XCTAssertEqual(state.data[2], 0x3971c188);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x82348678);
+	XCTAssertEqual(state.registers.data[2], 0x3971c188);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(48, self.machine->get_cycle_count());
 }
 
 - (void)testMULSZero {
-	[self performMULSd1:1 d2:0 ccr:Flag::Carry | Flag::Overflow | Flag::Extend];
+	[self performMULSd1:1 d2:0 ccr:ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(42, self.machine->get_cycle_count());
 }
 
@@ -1094,8 +1094,8 @@
 	[self performMULSConstant:0xffff d2:0xffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(44, self.machine->get_cycle_count());
 }
 
@@ -1103,8 +1103,8 @@
 	[self performMULSConstant:0x1fff d2:0x8fff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xf2005001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0xf2005001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(46, self.machine->get_cycle_count());
 }
 
@@ -1121,9 +1121,9 @@
 		0xc4c1		// MULU D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status |= ccr;
+	state.registers.data[1] = d1;
+	state.registers.data[2] = d2;
+	state.registers.status |= ccr;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1133,18 +1133,18 @@
 	[self performMULUd1:0x12345678 d2:0x12345678 ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x1d34d840);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[2], 0x1d34d840);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(54, self.machine->get_cycle_count());
 }
 
 - (void)testMULU_Dn_Zero {
-	[self performMULUd1:1 d2:0 ccr:Flag::Extend | Flag::Overflow | Flag::Carry];
+	[self performMULUd1:1 d2:0 ccr:ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(40, self.machine->get_cycle_count());
 }
 
@@ -1153,15 +1153,15 @@
 		0xc4fc, 0xffff		// MULU.W	#$ffff, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xffff;
-	state.status |= Flag::Extend | Flag::Overflow | Flag::Carry;
+	state.registers.data[2] = 0xffff;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xfffe0001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0xfffe0001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(74, self.machine->get_cycle_count());
 }
 
@@ -1178,7 +1178,7 @@
 		0x4400		// NEG.b D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
+	state.registers.data[0] = value;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1190,24 +1190,24 @@
 	[self performNEGb:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345688);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x12345688);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGb_00 {
 	[self performNEGb:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testNEGb_80 {
 	[self performNEGb:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345680);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12345680);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)testNEGw {
@@ -1215,15 +1215,15 @@
 		0x4440		// NEG.w D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = 0x12348000;
+	state.registers.data[0] = 0x12348000;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0x12348000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12348000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)performNEGl:(uint32_t)value {
@@ -1231,7 +1231,7 @@
 		0x4480		// NEG.l D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
+	state.registers.data[0] = value;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1243,16 +1243,16 @@
 	[self performNEGl:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xedcba988);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xedcba988);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGl_small {
 	[self performNEGl:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testNEGl_XXXl {
@@ -1268,7 +1268,7 @@
 	XCTAssertEqual(28, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*self.machine->ram_at(0x3002), 0xdcef);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 @end
@@ -1284,8 +1284,8 @@
 		0x4000		// NEGX.b D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = value;
+	state.registers.status |= ConditionCode::Extend;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1297,24 +1297,24 @@
 	[self performNEGXb:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345687);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x12345687);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXb_00 {
 	[self performNEGXb:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXb_80 {
 	[self performNEGXb:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234567f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x1234567f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)testNEGXw {
@@ -1322,16 +1322,16 @@
 		0x4040		// NEGX.w D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = 0x12348000;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = 0x12348000;
+	state.registers.status |= ConditionCode::Extend;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0x12347fff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12347fff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)performNEGXl:(uint32_t)value {
@@ -1339,8 +1339,8 @@
 		0x4080		// NEGX.l D0
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = value;
+	state.registers.status |= ConditionCode::Extend;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1352,16 +1352,16 @@
 	[self performNEGXl:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xedcba987);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xedcba987);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXl_small {
 	[self performNEGXl:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testNEGXl_XXXl {
@@ -1371,7 +1371,7 @@
 	*self.machine->ram_at(0x3000) = 0xf001;
 	*self.machine->ram_at(0x3002) = 0x2311;
 	auto state = self.machine->get_processor_state();
-	state.status |= Flag::Extend;
+	state.registers.status |= ConditionCode::Extend;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1380,7 +1380,7 @@
 	XCTAssertEqual(28, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*self.machine->ram_at(0x3002), 0xdcee);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 @end
@@ -1396,7 +1396,7 @@
 		0x0402, value		// SUB.b #value, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = d2;
+	state.registers.data[2] = d2;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
@@ -1408,32 +1408,32 @@
 	[self performSUBbIMM:0xff d2:0x9ae];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x9af);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x9af);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_82 {
 	[self performSUBbIMM:0x82 d2:0x0a];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x88);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Overflow | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x88);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_f0 {
 	[self performSUBbIMM:0xf0 d2:0x64];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x74);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x74);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_28 {
 	[self performSUBbIMM:0x28 d2:0xff96];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xff6e);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow);
+	XCTAssertEqual(state.registers.data[2], 0xff6e);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow);
 }
 
 - (void)testSUBb_PreDec {
@@ -1442,7 +1442,7 @@
 	});
 	self.machine->set_initial_stack_pointer(0x2002);
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x9c40;
+	state.registers.data[2] = 0x9c40;
 	*self.machine->ram_at(0x2000) = 0x2710;
 
 	self.machine->set_processor_state(state);
@@ -1450,8 +1450,8 @@
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(10, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x9c19);
-	XCTAssertEqual(state.stack_pointer(), 0x2000);
+	XCTAssertEqual(state.registers.data[2], 0x9c19);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2000);
 }
 
 // Omitted: SUB.w -(A6), D2, which is designed to trigger an address error.
@@ -1461,7 +1461,7 @@
 		0x9578, 0x3000		// SUB.w D2, ($3000).w
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x2711;
+	state.registers.data[2] = 0x2711;
 	*self.machine->ram_at(0x3000) = 0x759f;
 
 	self.machine->set_processor_state(state);
@@ -1469,8 +1469,8 @@
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x2711);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[2], 0x2711);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x4e8e);
 }
 
@@ -1479,8 +1479,8 @@
 		0x95ab, 0x0004		// SUB.l D2, 4(A3)
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x45fd5ab4;
-	state.address[3] = 0x3000;
+	state.registers.data[2] = 0x45fd5ab4;
+	state.registers.address[3] = 0x3000;
 	*self.machine->ram_at(0x3004) = 0x327a;
 	*self.machine->ram_at(0x3006) = 0x4ef3;
 
@@ -1489,9 +1489,9 @@
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(24, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x45fd5ab4);
-	XCTAssertEqual(state.address[3], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0x45fd5ab4);
+	XCTAssertEqual(state.registers.address[3], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(*self.machine->ram_at(0x3004), 0xec7c);
 	XCTAssertEqual(*self.machine->ram_at(0x3006), 0xf43f);
 }
@@ -1509,16 +1509,16 @@
 		0x95fc, 0x1234, 0x5678		// SUBA.l #$12345678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status |= Flag::ConditionCodes;
+	state.registers.address[2] = 0xae43ab1d;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0x9c0f54a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0x9c0f54a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testSUBAw_ImmPositive {
@@ -1526,15 +1526,15 @@
 		0x94fc, 0x5678		// SUBA.w #$5678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
+	state.registers.address[2] = 0xae43ab1d;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(12, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0xae4354a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xae4354a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBAw_ImmNegative {
@@ -1542,15 +1542,15 @@
 		0x94fc, 0xf678		// SUBA.w #$5678, A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
+	state.registers.address[2] = 0xae43ab1d;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(12, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0xae43b4a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xae43b4a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBAw_PreDec {
@@ -1558,7 +1558,7 @@
 		0x95e2		// SUBA.l -(A2), A2
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[2] = 0x2004;
+	state.registers.address[2] = 0x2004;
 	*self.machine->ram_at(0x2000) = 0x7002;
 	*self.machine->ram_at(0x2002) = 0x0000;
 
@@ -1567,8 +1567,8 @@
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0x8ffe2000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0x8ffe2000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 @end
@@ -1584,15 +1584,15 @@
 		0x0481, 0xf111, 0x1111		// SUBI.L #$f1111111, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x300021b3;
+	state.registers.data[1] = 0x300021b3;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x3eef10a2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x3eef10a2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 // Test of SUBI.W #$7aaa, ($3000).W omitted; that doesn't appear to be a valid instruction?
@@ -1610,15 +1610,15 @@
 		0x5f81		// SUBQ.L #$7, D1
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xffffffff;
+	state.registers.data[1] = 0xffffffff;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0xfffffff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xfffffff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 - (void)testSUBQw {
@@ -1626,15 +1626,15 @@
 		0x5f49		// SUBQ.W #$7, A1
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0xffff0001;
+	state.registers.address[1] = 0xffff0001;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[1], 0xfffefffa);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[1], 0xfffefffa);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBQb {
@@ -1648,7 +1648,7 @@
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0xff00);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 }
 
 @end
@@ -1664,18 +1664,18 @@
 		0x9581		// SUBX.l D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12345678;
-	state.data[2] = 0x12345678;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = 0x12345678;
+	state.registers.data[2] = 0x12345678;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testSUBXb_Dn {
@@ -1683,17 +1683,17 @@
 		0x9501		// SUBX.b D1, D2
 	});
 	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x80;
-	state.data[2] = 0x01;
+	state.registers.data[1] = 0x80;
+	state.registers.data[2] = 0x01;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x80);
-	XCTAssertEqual(state.data[2], 0x81);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x80);
+	XCTAssertEqual(state.registers.data[2], 0x81);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Overflow);
 }
 
 - (void)testSUBXl_PreDec {
@@ -1701,20 +1701,20 @@
 		0x9389		// SUBX.l -(A1), -(A1)
 	});
 	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
+	state.registers.address[1] = 0x3000;
 	*self.machine->ram_at(0x2ff8) = 0x1000;
 	*self.machine->ram_at(0x2ffa) = 0x0000;
 	*self.machine->ram_at(0x2ffc) = 0x7000;
 	*self.machine->ram_at(0x2ffe) = 0x1ff1;
-	state.status |= Flag::ConditionCodes;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
 	state = self.machine->get_processor_state();
 	XCTAssertEqual(30, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative );
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative );
 	XCTAssertEqual(*self.machine->ram_at(0x2ff8), 0x9fff);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffa), 0xe00e);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffc), 0x7000);
diff --git a/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm b/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm
index 1768a0195..84cff91bc 100644
--- a/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm	
@@ -33,15 +33,15 @@
 		0xc302,		// ABCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x1234567a;
-	state.data[2] = 0xf745ff78;
+	state.registers.data[1] = 0x1234567a;
+	state.registers.data[2] = 0xf745ff78;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssertEqual(state.data[1], 0x12345658);
-	XCTAssertEqual(state.data[2], 0xf745ff78);
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x12345658);
+	XCTAssertEqual(state.registers.data[2], 0xf745ff78);
 }
 
 - (void)testABCDZero {
@@ -49,16 +49,16 @@
 		0xc302,		// ABCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345600;
-	state.data[2] = 0x12345600;
-	state.status = Flag::Zero;
+	state.registers.data[1] = 0x12345600;
+	state.registers.data[2] = 0x12345600;
+	state.registers.status = ConditionCode::Zero;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Zero);
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.data[2], 0x12345600);
+	XCTAssert(state.registers.status & ConditionCode::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.data[2], 0x12345600);
 }
 
 - (void)testABCDNegative {
@@ -66,16 +66,16 @@
 		0xc302,		// ABCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345645;
-	state.data[2] = 0x12345654;
-	state.status = Flag::Zero;
+	state.registers.data[1] = 0x12345645;
+	state.registers.data[2] = 0x12345654;
+	state.registers.status = ConditionCode::Zero;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Negative);
-	XCTAssertEqual(state.data[1], 0x12345699);
-	XCTAssertEqual(state.data[2], 0x12345654);
+	XCTAssert(state.registers.status & ConditionCode::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345699);
+	XCTAssertEqual(state.registers.data[2], 0x12345654);
 }
 
 - (void)testABCDWithX {
@@ -83,16 +83,16 @@
 		0xc302,		// ABCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345645;
-	state.data[2] = 0x12345654;
-	state.status = Flag::Extend;
+	state.registers.data[1] = 0x12345645;
+	state.registers.data[2] = 0x12345654;
+	state.registers.status = ConditionCode::Extend;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.data[2], 0x12345654);
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.data[2], 0x12345654);
 }
 
 - (void)testABCDOverflow {
@@ -100,16 +100,16 @@
 		0xc302,		// ABCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x1234563e;
-	state.data[2] = 0x1234563e;
-	state.status = Flag::Extend;
+	state.registers.data[1] = 0x1234563e;
+	state.registers.data[2] = 0x1234563e;
+	state.registers.status = ConditionCode::Extend;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Overflow);
-	XCTAssertEqual(state.data[1], 0x12345683);
-	XCTAssertEqual(state.data[2], 0x1234563e);
+	XCTAssert(state.registers.status & ConditionCode::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x12345683);
+	XCTAssertEqual(state.registers.data[2], 0x1234563e);
 }
 
 - (void)testABCDPredecDifferent {
@@ -120,17 +120,17 @@
 	*_machine->ram_at(0x4000) = 0x1900;
 
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3001;
-	state.address[2] = 0x4001;
-	state.status = Flag::Extend;
+	state.registers.address[1] = 0x3001;
+	state.registers.address[2] = 0x4001;
+	state.registers.status = ConditionCode::Extend;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssert(state.status & Flag::Extend);
-	XCTAssertEqual(state.address[1], 0x3000);
-	XCTAssertEqual(state.address[2], 0x4000);
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssert(state.registers.status & ConditionCode::Extend);
+	XCTAssertEqual(state.registers.address[1], 0x3000);
+	XCTAssertEqual(state.registers.address[2], 0x4000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x2200);
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);
 }
@@ -142,15 +142,15 @@
 	*_machine->ram_at(0x3000) = 0x19a2;
 
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3002;
-	state.status = Flag::Extend;
+	state.registers.address[1] = 0x3002;
+	state.registers.status = ConditionCode::Extend;
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssert(state.status & Flag::Extend);
-	XCTAssertEqual(state.address[1], 0x3000);
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssert(state.registers.status & ConditionCode::Extend);
+	XCTAssertEqual(state.registers.address[1], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x22a2);
 }
 
@@ -161,8 +161,8 @@
 		0x4801		// NBCD D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= ccr;
-	state.data[1] = d1;
+	state.registers.status |= ccr;
+	state.registers.data[1] = d1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -174,32 +174,32 @@
 	[self performNBCDd1:0x7a ccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testNBCD_Dn_extend {
-	[self performNBCDd1:0x1234567a ccr:Flag::Extend | Flag::Zero];
+	[self performNBCDd1:0x1234567a ccr:ConditionCode::Extend | ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234561f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x1234561f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testNBCD_Dn_zero {
-	[self performNBCDd1:0x12345600 ccr:Flag::Zero];
+	[self performNBCDd1:0x12345600 ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testNBCD_Dn_negative {
-	[self performNBCDd1:0x123456ff ccr:Flag::Extend | Flag::Zero];
+	[self performNBCDd1:0x123456ff ccr:ConditionCode::Extend | ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234569a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x1234569a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testNBCD_Dn_XXXw {
@@ -213,7 +213,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(16, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x9900);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 // MARK: SBCD
@@ -223,48 +223,48 @@
 		0x8302		// SBCD D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= ccr;
-	state.data[1] = d1;
-	state.data[2] = d2;
+	state.registers.status |= ccr;
+	state.registers.data[1] = d1;
+	state.registers.data[2] = d2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(6, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], d2);
+	XCTAssertEqual(state.registers.data[2], d2);
 }
 
 - (void)testSBCD_Dn {
-	[self performSBCDd1:0x12345689 d2:0xf745ff78 ccr:Flag::Zero];
+	[self performSBCDd1:0x12345689 d2:0xf745ff78 ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345611);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345611);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSBCD_Dn_zero {
-	[self performSBCDd1:0x123456ff d2:0xf745ffff ccr:Flag::Zero];
+	[self performSBCDd1:0x123456ff d2:0xf745ffff ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testSBCD_Dn_negative {
-	[self performSBCDd1:0x12345634 d2:0xf745ff45 ccr:Flag::Extend];
+	[self performSBCDd1:0x12345634 d2:0xf745ff45 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345688);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345688);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testSBCD_Dn_overflow {
-	[self performSBCDd1:0x123456a9 d2:0xf745ffff ccr:Flag::Extend];
+	[self performSBCDd1:0x123456a9 d2:0xf745ffff ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345643);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x12345643);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testSBCD_Dn_PreDec {
@@ -274,9 +274,9 @@
 	*_machine->ram_at(0x3000) = 0xa200;
 	*_machine->ram_at(0x4000) = 0x1900;
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3001;
-	state.address[2] = 0x4001;
-	state.status |= Flag::Extend;
+	state.registers.address[1] = 0x3001;
+	state.registers.address[2] = 0x4001;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -285,7 +285,7 @@
 	XCTAssertEqual(18, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x8200);
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 @end
diff --git a/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm b/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm
index 51bea342f..a3dcd8420 100644
--- a/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm	
@@ -33,16 +33,16 @@
 		0xc604		// AND.b D4, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54ff7856;
-	state.data[4] = 0x9853abcd;
+	state.registers.data[3] = 0x54ff7856;
+	state.registers.data[4] = 0x9853abcd;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff7844);
-	XCTAssertEqual(state.data[4], 0x9853abcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff7844);
+	XCTAssertEqual(state.registers.data[4], 0x9853abcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 4);
 }
 
@@ -51,16 +51,16 @@
 		0xc644		// AND.w D4, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[4] = 0x9853fbcd;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[4] = 0x9853fbcd;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff844);
-	XCTAssertEqual(state.data[4], 0x9853fbcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[3], 0x54fff844);
+	XCTAssertEqual(state.registers.data[4], 0x9853fbcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(_machine->get_cycle_count(), 4);
 }
 
@@ -69,16 +69,16 @@
 		0xc684		// AND.l D4, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[4] = 0x9853fbcd;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[4] = 0x9853fbcd;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x1053f844);
-	XCTAssertEqual(state.data[4], 0x9853fbcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x1053f844);
+	XCTAssertEqual(state.registers.data[4], 0x9853fbcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -87,8 +87,8 @@
 		opcode
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
 
@@ -98,15 +98,15 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
-	XCTAssertEqual(state.address[4], 0x3000);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
 }
 
 - (void)testANDb_Ind {
 	[self performANDx_Ind:0xc614];	// AND.b (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -114,8 +114,8 @@
 	[self performANDx_Ind:0xc654];	// AND.w (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0052);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0052);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -123,8 +123,8 @@
 	[self performANDx_Ind:0xc694];	// AND.l (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -133,8 +133,8 @@
 		opcode		// AND.B (A4)+, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
 
@@ -146,9 +146,9 @@
 	[self performANDx_PostInc:0xc61c]; // AND.B (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.address[4], 0x3001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.address[4], 0x3001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -158,7 +158,7 @@
 	});
 	_machine->set_initial_stack_pointer(0x3000);
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
 
@@ -166,9 +166,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.stack_pointer(), 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -176,9 +176,9 @@
 	[self performANDx_PostInc:0xc65c]; // AND.w (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0052);
-	XCTAssertEqual(state.address[4], 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0052);
+	XCTAssertEqual(state.registers.address[4], 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -186,9 +186,9 @@
 	[self performANDx_PostInc:0xc69c]; // AND.l (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.address[4], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.address[4], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -199,8 +199,8 @@
 		0xc6a4	// AND.l -(A4), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3004;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3004;
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
 
@@ -210,9 +210,9 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -221,8 +221,8 @@
 		0xc6ac, 0xfffa	// AND.l -6(A4), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3006;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -232,9 +232,9 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3006);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -243,9 +243,9 @@
 		0xc6b4, 0x6006	// AND.l 6(A4, D6.W), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xfffffffd;
-	state.address[4] = 0x2ffd;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[6] = 0xfffffffd;
+	state.registers.address[4] = 0x2ffd;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -255,10 +255,10 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x2ffd);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xfffffffd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x2ffd);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xfffffffd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -267,9 +267,9 @@
 		0xc6b4, 0x60fe	// AND.l -2(A4, D6.W), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xf001fffd;
-	state.address[4] = 0x3005;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[6] = 0xf001fffd;
+	state.registers.address[4] = 0x3005;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -279,10 +279,10 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3005);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xf001fffd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3005);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xf001fffd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -291,9 +291,9 @@
 		0xc6b4, 0x6801	// AND.l 6(A4, D6.W), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xffffffff;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[6] = 0xffffffff;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -303,10 +303,10 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -315,7 +315,7 @@
 		0xc6b8, 0x3000	// AND.l $3000.w, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -325,8 +325,8 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -335,7 +335,7 @@
 		0xc6b9, 0x0001, 0x1170	// AND.L $11170.l, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 	*_machine->ram_at(0x11170) = 0x1253;
 	*_machine->ram_at(0x11172) = 0xfb34;
 
@@ -345,8 +345,8 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x11170), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x11172), 0xfb34);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -355,7 +355,7 @@
 		0xc6ba, 0xfffa	// AND.l -6(PC), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 	*_machine->ram_at(0xffc) = 0x383c;
 	*_machine->ram_at(0xffe) = 0x1234;
 
@@ -365,8 +365,8 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
 	XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
-	XCTAssertEqual(state.data[3], 0x103c1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x103c1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -375,8 +375,8 @@
 		0xc6bb, 0x10f6	// and.l -10(PC), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[1] = 4;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.data[1] = 4;
 	*_machine->ram_at(0xffc) = 0x383c;
 	*_machine->ram_at(0xffe) = 0x1234;
 
@@ -386,8 +386,8 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
 	XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
-	XCTAssertEqual(state.data[3], 0x103c1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x103c1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -396,14 +396,14 @@
 		0xc63c, 0x0034	// AND.b #$34, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -412,14 +412,14 @@
 		0xc67c, 0x1234	// AND.w #$1234, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -428,14 +428,14 @@
 		0xc6bc, 0x3456, 0x1234	// AND.l #$34561234, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	state.registers.data[3] = 0x54fff856;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x14561014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x14561014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -444,8 +444,8 @@
 		0xc794	// AND.l D3, (A4)
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
 
@@ -453,9 +453,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -466,8 +466,8 @@
 		0xc79c	// AND.l D3, (A4)+
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
 
@@ -475,9 +475,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -488,8 +488,8 @@
 		0xc7a4	// AND.l D3, -(A4)
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x2ffc) = 0x1253;
 	*_machine->ram_at(0x2ffe) = 0xfb03;
 
@@ -497,9 +497,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0xf802);
 	XCTAssertEqual(22, _machine->get_cycle_count());
@@ -510,8 +510,8 @@
 		0xc7ac, 0x0002	// AND.l D3, 2(A4)
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3002) = 0x1253;
 	*_machine->ram_at(0x3004) = 0xfb03;
 
@@ -519,9 +519,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xf802);
 	XCTAssertEqual(24, _machine->get_cycle_count());
@@ -532,8 +532,8 @@
 		0xc7b8, 0x3000	// AND.l D3, ($3000).w
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
 
@@ -541,9 +541,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(24, _machine->get_cycle_count());
@@ -556,22 +556,22 @@
 		0x0340		// BCHG D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = d1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBCHG_D0D1_0 {
 	[self performBCHGD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345679);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345679);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -579,8 +579,8 @@
 	[self performBCHGD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345278);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345278);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -588,8 +588,8 @@
 	[self performBCHGD0D1:48];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12355678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12355678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -598,16 +598,16 @@
 		0x0350		// BCHG D1, (A0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	state.registers.address[0] = 0x3000;
+	state.registers.data[1] = d1;
 	*_machine->ram_at(0x3000) = 0x7800;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -615,7 +615,7 @@
 	[self performBCHGD1Ind:48];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7900);
 }
 
@@ -623,7 +623,7 @@
 	[self performBCHGD1Ind:7];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xf800);
 }
 
@@ -632,7 +632,7 @@
 		0x0840, immediate		// BCHG #, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
+	state.registers.data[0] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -642,8 +642,8 @@
 	[self performBCHGImm:31];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x92345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x92345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -651,8 +651,8 @@
 	[self performBCHGImm:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345668);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345668);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -665,7 +665,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
 }
@@ -677,22 +677,22 @@
 		0x0380		// BCLR D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = d1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBCLR_D0D1_0 {
 	[self performBCLRD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -700,8 +700,8 @@
 	[self performBCLRD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345278);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345278);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -709,8 +709,8 @@
 	[self performBCLRD0D1:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12305678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12305678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -719,16 +719,16 @@
 		0x0390		// BCLR D1, (A0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	state.registers.address[0] = 0x3000;
+	state.registers.data[1] = d1;
 	*_machine->ram_at(0x3000) = 0x7800;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -736,7 +736,7 @@
 	[self performBCLRD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
 
@@ -744,7 +744,7 @@
 	[self performBCLRD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7000);
 }
 
@@ -753,20 +753,20 @@
 		0x0880, immediate		// BCLR #, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
+	state.registers.data[0] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBCLR_Imm_28 {
 	[self performBCLRImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x02345678);
+	XCTAssertEqual(state.registers.data[0], 0x02345678);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -774,7 +774,7 @@
 	[self performBCLRImm:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345668);
+	XCTAssertEqual(state.registers.data[0], 0x12345668);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -787,7 +787,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
 }
@@ -799,22 +799,22 @@
 		0x03c0		// BSET D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = d1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBSET_D0D1_0 {
 	[self performBSETD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345679);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345679);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -822,8 +822,8 @@
 	[self performBSETD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -831,8 +831,8 @@
 	[self performBSETD0D1:49];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12365678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12365678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -841,16 +841,16 @@
 		0x03d0		// BSET D1, (A0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	state.registers.address[0] = 0x3000;
+	state.registers.data[1] = d1;
 	*_machine->ram_at(0x3000) = 0x7800;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -858,7 +858,7 @@
 	[self performBSETD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7c00);
 }
 
@@ -866,7 +866,7 @@
 	[self performBSETD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
 
@@ -875,7 +875,7 @@
 		0x08c0, immediate		// BSET #, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
+	state.registers.data[0] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -885,8 +885,8 @@
 	[self performBSETImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -894,8 +894,8 @@
 	[self performBSETImm:2];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234567c);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x1234567c);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -908,7 +908,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -920,15 +920,15 @@
 		0x0300		// BTST D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = d1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], d1);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -936,21 +936,21 @@
 	[self performBTSTD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_D0D1_10 {
 	[self performBTSTD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBTST_D0D1_49 {
 	[self performBTSTD0D1:49];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)performBTSTD1Ind:(uint32_t)d1 {
@@ -958,16 +958,16 @@
 		0x0310		// BTST D1, (A0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	state.registers.address[0] = 0x3000;
+	state.registers.data[1] = d1;
 	*_machine->ram_at(0x3000) = 0x7800;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -976,14 +976,14 @@
 	[self performBTSTD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_D1Ind_3 {
 	[self performBTSTD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performBTSTImm:(uint16_t)immediate {
@@ -991,13 +991,13 @@
 		0x0800, immediate		// BTST #, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
+	state.registers.data[0] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -1005,14 +1005,14 @@
 	[self performBTSTImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBTST_Imm_2 {
 	[self performBTSTImm:2];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_ImmWWWx {
@@ -1024,7 +1024,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 16);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -1038,14 +1038,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345610);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345610);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1062,7 +1062,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1073,13 +1073,13 @@
 		0x023c, 0x001b		// ANDI.b #$1b, CCR
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
+	state.registers.status |= 0xc;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc & 0x1b);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc & 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1094,7 +1094,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1107,7 +1107,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1119,16 +1119,16 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[3] = 0x54ff0056;
-	state.data[4] = 0x9853abcd;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	state.registers.data[3] = 0x54ff0056;
+	state.registers.data[4] = 0x9853abcd;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0056);
-	XCTAssertEqual(state.data[4], 0x9853ab9b);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0056);
+	XCTAssertEqual(state.registers.data[4], 0x9853ab9b);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1138,8 +1138,8 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.data[3] = 0x54ff0056;
+	state.registers.address[2] = 0x3000;
+	state.registers.data[3] = 0x54ff0056;
 	*_machine->ram_at(0x3000) = 0x0f0f;
 	*_machine->ram_at(0x3002) = 0x0f11;
 
@@ -1147,11 +1147,11 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0056);
-	XCTAssertEqual(state.address[2], 0x3000);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0056);
+	XCTAssertEqual(state.registers.address[2], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x5bf0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0f47);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1163,14 +1163,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234566a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x1234566a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1187,7 +1187,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xffff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1199,13 +1199,13 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
+	state.registers.status |= 0xc;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc ^ 0x1b);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc ^ 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1220,7 +1220,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1233,7 +1233,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1244,14 +1244,14 @@
 		0x4600		// NOT.B D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
+	state.registers.data[0] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345687);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x12345687);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1260,15 +1260,15 @@
 		0x4640		// NOT.w D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12340000;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[0] = 0x12340000;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234ffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x1234ffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1277,15 +1277,15 @@
 		0x4680		// NOT.l D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xffffff00;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[0] = 0xffffff00;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x000000ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x000000ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -1296,7 +1296,7 @@
 	*_machine->ram_at(0x3000) = 0xf001;
 	*_machine->ram_at(0x3002) = 0x2311;
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -1304,7 +1304,7 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xdcee);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -1315,17 +1315,17 @@
 		0x8604		// OR.b D4, D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54ff0056;
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
+	state.registers.data[3] = 0x54ff0056;
+	state.registers.data[4] = 0x9853abcd;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff00df);
-	XCTAssertEqual(state.data[4], 0x9853abcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[3], 0x54ff00df);
+	XCTAssertEqual(state.registers.data[4], 0x9853abcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1334,8 +1334,8 @@
 		0x86ac, 0xfffa		// OR.l -6(A4), D3
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3006;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -1343,11 +1343,11 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x56fffb76);
-	XCTAssertEqual(state.address[4], 0x3006);
+	XCTAssertEqual(state.registers.data[3], 0x56fffb76);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -1356,8 +1356,8 @@
 		0x87ac, 0xfffa		// OR.l D3, -6(A4)
 	});
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	state.registers.data[3] = 0x54fff856;
+	state.registers.address[4] = 0x3006;
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
 
@@ -1365,11 +1365,11 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3006);
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x56ff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb76);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -1381,14 +1381,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234567a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x1234567a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1405,7 +1405,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xffff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1417,13 +1417,13 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
+	state.registers.status |= 0xc;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc | 0x1b);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc | 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1438,7 +1438,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1451,7 +1451,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1463,13 +1463,13 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[0] = d0;
+	state.registers.data[0] = d0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, ccr);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ccr);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1478,7 +1478,7 @@
 }
 
 - (void)testTAS_Dn_set {
-	[self performTASDnd0:0x123456f0 expectedCCR:Flag::Negative];
+	[self performTASDnd0:0x123456f0 expectedCCR:ConditionCode::Negative];
 }
 
 - (void)testTAS_XXXl {
@@ -1488,13 +1488,13 @@
 	*_machine->ram_at(0x3000) = 0x1100;
 
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::ConditionCodes;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x9100);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
diff --git a/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm b/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm
index 947abf8fe..5e9559171 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm	
@@ -49,7 +49,7 @@
 	[self performBccb:0x6200];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -57,7 +57,7 @@
 	[self performBccb:0x6500];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -65,7 +65,7 @@
 	[self performBccw:0x6200];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -73,7 +73,7 @@
 	[self performBccw:0x6500];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -87,7 +87,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1006 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1006 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -99,7 +99,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1006 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1006 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -114,9 +114,9 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0x1004);
 
@@ -132,9 +132,9 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0x1002);
 
@@ -148,25 +148,25 @@
 		0x4581		// CHK D1, D2
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status |= Flag::ConditionCodes;
+	state.registers.data[1] = d1;
+	state.registers.data[2] = d2;
+	state.registers.status |= ConditionCode::AllConditions;
 
 	_machine->set_initial_stack_pointer(0);
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.data[2], d2);
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.data[2], d2);
 }
 
 - (void)testCHK_1111v1111 {
 	[self performCHKd1:0x1111 d2:0x1111];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -174,8 +174,8 @@
 	[self performCHKd1:0x1111 d2:0x0000];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -183,9 +183,9 @@
 	[self performCHKd1:0x8000 d2:0x8001];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0xfffffffa);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0xfffffffa);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(42, _machine->get_cycle_count());
 }
 
@@ -193,8 +193,8 @@
 	[self performCHKd1:0x8000 d2:0x8000];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(44, _machine->get_cycle_count());
 }
 
@@ -205,15 +205,15 @@
 		opcode, 0x0008		// DBcc D2, +8
 	});
 	auto state = _machine->get_processor_state();
-	state.status = status;
-	state.data[2] = 1;
+	state.registers.status = status;
+	state.registers.data[2] = 1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[2], d2Output);
-	XCTAssertEqual(state.status, status);
+	XCTAssertEqual(state.registers.data[2], d2Output);
+	XCTAssertEqual(state.registers.status, status);
 }
 
 - (void)testDBT {
@@ -229,27 +229,27 @@
 }
 
 - (void)testDBHI_Carry {
-	[self performDBccTestOpcode:0x52ca status:Flag::Carry d2Outcome:0];
+	[self performDBccTestOpcode:0x52ca status:ConditionCode::Carry d2Outcome:0];
 }
 
 - (void)testDBHI_Zero {
-	[self performDBccTestOpcode:0x52ca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x52ca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBLS_CarryOverflow {
-	[self performDBccTestOpcode:0x53ca status:Flag::Carry | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Carry | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBLS_Carry {
-	[self performDBccTestOpcode:0x53ca status:Flag::Carry d2Outcome:1];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Carry d2Outcome:1];
 }
 
 - (void)testDBLS_Overflow {
-	[self performDBccTestOpcode:0x53ca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBCC_Carry {
-	[self performDBccTestOpcode:0x54ca status:Flag::Carry d2Outcome:0];
+	[self performDBccTestOpcode:0x54ca status:ConditionCode::Carry d2Outcome:0];
 }
 
 - (void)testDBCC {
@@ -261,7 +261,7 @@
 }
 
 - (void)testDBCS_Carry {
-	[self performDBccTestOpcode:0x55ca status:Flag::Carry d2Outcome:1];
+	[self performDBccTestOpcode:0x55ca status:ConditionCode::Carry d2Outcome:1];
 }
 
 - (void)testDBNE {
@@ -269,7 +269,7 @@
 }
 
 - (void)testDBNE_Zero {
-	[self performDBccTestOpcode:0x56ca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x56ca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBEQ {
@@ -277,7 +277,7 @@
 }
 
 - (void)testDBEQ_Zero {
-	[self performDBccTestOpcode:0x57ca status:Flag::Zero d2Outcome:1];
+	[self performDBccTestOpcode:0x57ca status:ConditionCode::Zero d2Outcome:1];
 }
 
 - (void)testDBVC {
@@ -285,7 +285,7 @@
 }
 
 - (void)testDBVC_Overflow {
-	[self performDBccTestOpcode:0x58ca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x58ca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBVS {
@@ -293,7 +293,7 @@
 }
 
 - (void)testDBVS_Overflow {
-	[self performDBccTestOpcode:0x59ca status:Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x59ca status:ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBPL {
@@ -301,7 +301,7 @@
 }
 
 - (void)testDBPL_Negative {
-	[self performDBccTestOpcode:0x5aca status:Flag::Negative d2Outcome:0];
+	[self performDBccTestOpcode:0x5aca status:ConditionCode::Negative d2Outcome:0];
 }
 
 - (void)testDBMI {
@@ -309,11 +309,11 @@
 }
 
 - (void)testDBMI_Negative {
-	[self performDBccTestOpcode:0x5bca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5bca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBGE_NegativeOverflow {
-	[self performDBccTestOpcode:0x5cca status:Flag::Negative | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGE {
@@ -321,15 +321,15 @@
 }
 
 - (void)testDBGE_Negative {
-	[self performDBccTestOpcode:0x5cca status:Flag::Negative d2Outcome:0];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Negative d2Outcome:0];
 }
 
 - (void)testDBGE_Overflow {
-	[self performDBccTestOpcode:0x5cca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBLT_NegativeOverflow {
-	[self performDBccTestOpcode:0x5dca status:Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBLT {
@@ -337,11 +337,11 @@
 }
 
 - (void)testDBLT_Negative {
-	[self performDBccTestOpcode:0x5dca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBLT_Overflow {
-	[self performDBccTestOpcode:0x5dca status:Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGT {
@@ -349,15 +349,15 @@
 }
 
 - (void)testDBGT_ZeroNegativeOverflow {
-	[self performDBccTestOpcode:0x5eca status:Flag::Zero | Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Zero | ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBGT_NegativeOverflow {
-	[self performDBccTestOpcode:0x5eca status:Flag::Negative | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGT_Zero {
-	[self performDBccTestOpcode:0x5eca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBLE {
@@ -365,15 +365,15 @@
 }
 
 - (void)testDBLE_Zero {
-	[self performDBccTestOpcode:0x5fca status:Flag::Zero d2Outcome:1];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Zero d2Outcome:1];
 }
 
 - (void)testDBLE_Negative {
-	[self performDBccTestOpcode:0x5fca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBLE_NegativeOverflow {
-	[self performDBccTestOpcode:0x5fca status:Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 /* Further DBF tests omitted; they seemed to be duplicative, assuming I'm not suffering a failure of comprehension. */
@@ -386,14 +386,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
+	state.registers.address[1] = 0x3000;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3000);
-	XCTAssertEqual(state.program_counter, 0x3000 + 4);
+	XCTAssertEqual(state.registers.address[1], 0x3000);
+	XCTAssertEqual(state.registers.program_counter, 0x3000 + 4);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -405,7 +405,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x100c + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x100c + 4);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -420,8 +420,8 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1ffc);
-	XCTAssertEqual(state.program_counter, 0x100c + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1ffc);
+	XCTAssertEqual(state.registers.program_counter, 0x100c + 4);
 	XCTAssertEqual(*_machine->ram_at(0x1ffc), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1ffe), 0x1004);
 	XCTAssertEqual(18, _machine->get_cycle_count());
@@ -436,8 +436,8 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1ffc);
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1ffc);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(*_machine->ram_at(0x1ffc), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1ffe), 0x1006);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -467,9 +467,9 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x2006);
-	XCTAssertEqual(state.program_counter, 0x10);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2006);
+	XCTAssertEqual(state.registers.program_counter, 0x10);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -486,8 +486,8 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x2004);
-	XCTAssertEqual(state.program_counter, 0x000c + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2004);
+	XCTAssertEqual(state.registers.program_counter, 0x000c + 4);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -498,9 +498,9 @@
 		0x4e41		// TRAP #1
 	});
 	auto state = _machine->get_processor_state();
-	state.status = 0x700;
-	state.user_stack_pointer = 0x200;
-	state.supervisor_stack_pointer = 0x206;
+	state.registers.status = 0x700;
+	state.registers.user_stack_pointer = 0x200;
+	state.registers.supervisor_stack_pointer = 0x206;
 	*_machine->ram_at(0x84) = 0xfffe;
 	*_machine->ram_at(0xfffe) = 0x4e71;
 
@@ -508,11 +508,11 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status, 0x2700);
+	XCTAssertEqual(state.registers.status, 0x2700);
 	XCTAssertEqual(*_machine->ram_at(0x200), 0x700);
 	XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x204), 0x1002);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x200);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x200);
 	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -525,8 +525,8 @@
 	_machine->set_initial_stack_pointer(0x206);
 
 	auto state = _machine->get_processor_state();
-	state.status = 0x702;
-	state.supervisor_stack_pointer = 0x206;
+	state.registers.status = 0x702;
+	state.registers.supervisor_stack_pointer = 0x206;
 	*_machine->ram_at(0x1e) = 0xfffe;
 	*_machine->ram_at(0xfffe) = 0x4e71;
 
@@ -534,8 +534,8 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status, 0x2702);
-	XCTAssertEqual(state.stack_pointer(), 0x200);
+	XCTAssertEqual(state.registers.status, 0x2702);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x200);
 	XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x204), 0x1002);
 	XCTAssertEqual(*_machine->ram_at(0x200), 0x702);
@@ -550,7 +550,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm b/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm
index 27fbd04ac..6704fd4ec 100644
--- a/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm	
@@ -33,15 +33,15 @@
 		0x4244		// CLR.w D4
 	});
 	auto state = _machine->get_processor_state();
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
+	state.registers.data[4] = 0x9853abcd;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[4], 0x98530000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[4], 0x98530000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -50,15 +50,15 @@
 		0x4284		// CLR.l D4
 	});
 	auto state = _machine->get_processor_state();
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
+	state.registers.data[4] = 0x9853abcd;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[4], 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[4], 0x0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -69,7 +69,7 @@
 	*_machine->ram_at(0x186a0) = 0x9853;
 	*_machine->ram_at(0x186a2) = 0xabcd;
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -77,7 +77,7 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x186a0), 0x0);
 	XCTAssertEqual(*_machine->ram_at(0x186a2), 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -88,7 +88,7 @@
 	*_machine->ram_at(0x186a0) = 0x9853;
 	*_machine->ram_at(0x186a2) = 0xabcd;
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -96,7 +96,7 @@
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x186a0), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x186a2), 0xabcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -108,15 +108,15 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x11111111;
-	state.data[2] = 0x22222222;
+	state.registers.data[1] = 0x11111111;
+	state.registers.data[2] = 0x22222222;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x22222222);
-	XCTAssertEqual(state.data[2], 0x11111111);
+	XCTAssertEqual(state.registers.data[1], 0x22222222);
+	XCTAssertEqual(state.registers.data[2], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -126,15 +126,15 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
-	state.address[2] = 0x22222222;
+	state.registers.address[1] = 0x11111111;
+	state.registers.address[2] = 0x22222222;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x22222222);
-	XCTAssertEqual(state.address[2], 0x11111111);
+	XCTAssertEqual(state.registers.address[1], 0x22222222);
+	XCTAssertEqual(state.registers.address[2], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -144,15 +144,15 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x11111111;
-	state.address[1] = 0x22222222;
+	state.registers.data[1] = 0x11111111;
+	state.registers.address[1] = 0x22222222;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x22222222);
-	XCTAssertEqual(state.address[1], 0x11111111);
+	XCTAssertEqual(state.registers.data[1], 0x22222222);
+	XCTAssertEqual(state.registers.address[1], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -166,7 +166,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[0], 0xc);
+	XCTAssertEqual(state.registers.address[0], 0xc);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -178,7 +178,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[0], 0xc000d);
+	XCTAssertEqual(state.registers.address[0], 0xc000d);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -188,14 +188,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
+	state.registers.address[2] = 0xc000d;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc000d);
-	XCTAssertEqual(state.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.address[1], 0xc000d);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -205,14 +205,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
+	state.registers.address[2] = 0xc000d;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc000c);
-	XCTAssertEqual(state.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.address[1], 0xc000c);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -222,16 +222,16 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-	state.data[7] = 0x10000022;
+	state.registers.address[2] = 0xc000d;
+	state.registers.data[7] = 0x10000022;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc0031);
-	XCTAssertEqual(state.address[2], 0xc000d);
-	XCTAssertEqual(state.data[7], 0x10000022);
+	XCTAssertEqual(state.registers.address[1], 0xc0031);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.data[7], 0x10000022);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -241,16 +241,16 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-	state.data[7] = 0x10000022;
+	state.registers.address[2] = 0xc000d;
+	state.registers.data[7] = 0x10000022;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x100c0031);
-	XCTAssertEqual(state.address[2], 0xc000d);
-	XCTAssertEqual(state.data[7], 0x10000022);
+	XCTAssertEqual(state.registers.address[1], 0x100c0031);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.data[7], 0x10000022);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -260,13 +260,13 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
+	state.registers.address[2] = 0xc000d;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xFFFFFFFA);
+	XCTAssertEqual(state.registers.address[1], 0xFFFFFFFA);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -276,14 +276,14 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.data[3] = 0x2;
+	state.registers.data[3] = 0x2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x1002);
-	XCTAssertEqual(state.data[3], 0x2);
+	XCTAssertEqual(state.registers.address[1], 0x1002);
+	XCTAssertEqual(state.registers.data[3], 0x2);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -294,15 +294,15 @@
 		0x4e51, 0x0005		// LINK a1, #5
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
+	state.registers.address[1] = 0x11111111;
 	_machine->set_initial_stack_pointer(0x22222222);
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2222221e);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x22222223);
+	XCTAssertEqual(state.registers.address[1], 0x2222221e);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x22222223);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x1111);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -317,7 +317,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x22222223);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x22222223);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x2222);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x221e);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -328,15 +328,15 @@
 		0x4e51, 0x8000		// LINK a1, #$8000
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
+	state.registers.address[1] = 0x11111111;
 	_machine->set_initial_stack_pointer(0x22222222);
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2222221e);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x2221a21e);
+	XCTAssertEqual(state.registers.address[1], 0x2222221e);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x2221a21e);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x1111);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -349,17 +349,17 @@
 		0x48e1, 0xc000		// MOVEM.L D0-D1, -(A1)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.data[0] = 0x12345678;
-	state.data[1] = 0x87654321;
+	state.registers.address[1] = 0x3000;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = 0x87654321;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], 0x87654321);
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], 0x87654321);
 	XCTAssertEqual(*_machine->ram_at(0x2ff8), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x2ffa), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0x8765);
@@ -372,17 +372,17 @@
 		0x48e1, 0xc040		// MOVEM.L D0-D1/A1, -(A1)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.data[0] = 0x12345678;
-	state.data[1] = 0x87654321;
+	state.registers.address[1] = 0x3000;
+	state.registers.data[0] = 0x12345678;
+	state.registers.data[1] = 0x87654321;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff4);
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], 0x87654321);
+	XCTAssertEqual(state.registers.address[1], 0x2ff4);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], 0x87654321);
 	XCTAssertEqual(*_machine->ram_at(0x2ff4), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x2ff6), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x2ff8), 0x8765);
@@ -398,17 +398,17 @@
 	});
 	auto state = _machine->get_processor_state();
 	for(int c = 0; c < 8; ++c)
-		state.data[c] = (c+1) * 0x11111111;
+		state.registers.data[c] = (c+1) * 0x11111111;
 	for(int c = 0; c < 7; ++c)
-		state.address[c] = ((c < 4) ? (c + 9) : (c + 8)) * 0x11111111;
-	state.address[4] = 0x4000;
+		state.registers.address[c] = ((c < 4) ? (c + 9) : (c + 8)) * 0x11111111;
+	state.registers.address[4] = 0x4000;
 	_machine->set_initial_stack_pointer(0xffffffff);
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[4], 0x3fc0);
+	XCTAssertEqual(state.registers.address[4], 0x3fc0);
 
 	const uint32_t expected_values[] = {
 		0xffffffff, 0xeeeeeeee, 0xdddddddd, 0x00004000,
@@ -431,18 +431,18 @@
 		0x48a4, 0x0800		// MOVEM.W D4, -(A4)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[4] = 0x4000;
-	state.data[4] = 0x111a1111;
-	state.data[0] = 0xffffffff;
+	state.registers.address[4] = 0x4000;
+	state.registers.data[4] = 0x111a1111;
+	state.registers.data[0] = 0xffffffff;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.address[4], 0x3ffe);
-	XCTAssertEqual(state.data[0], 0xffffffff);
-	XCTAssertEqual(state.data[4], 0x111a1111);
+	XCTAssertEqual(state.registers.address[4], 0x3ffe);
+	XCTAssertEqual(state.registers.data[0], 0xffffffff);
+	XCTAssertEqual(state.registers.data[4], 0x111a1111);
 
 	XCTAssertEqual(*_machine->ram_at(0x3ffe), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x3ffc), 0x0000);
@@ -457,7 +457,7 @@
 		0x4cd9, 0x0606		// MOVEM.l (A1)+, D1-D2/A1-A2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
+	state.registers.address[1] = 0x4000;
 	*_machine->ram_at(0x4000) = 0x1111;
 	*_machine->ram_at(0x4002) = 0x1111;
 	*_machine->ram_at(0x4004) = 0x2222;
@@ -470,10 +470,10 @@
 
 	state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0x11111111);
-	XCTAssertEqual(state.data[2], 0x22222222);
-	XCTAssertEqual(state.address[1], 0x4010);
-	XCTAssertEqual(state.address[2], 0x33333333);
+	XCTAssertEqual(state.registers.data[1], 0x11111111);
+	XCTAssertEqual(state.registers.data[2], 0x22222222);
+	XCTAssertEqual(state.registers.address[1], 0x4010);
+	XCTAssertEqual(state.registers.address[2], 0x33333333);
 
 	XCTAssertEqual(44, _machine->get_cycle_count());
 }
@@ -483,7 +483,7 @@
 		0x4c99, 0x0002		// MOVEM.w (A1)+, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
+	state.registers.address[1] = 0x4000;
 	*_machine->ram_at(0x4000) = 0x8000;
 
 	_machine->set_processor_state(state);
@@ -491,8 +491,8 @@
 
 	state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0xffff8000);
-	XCTAssertEqual(state.address[1], 0x4002);
+	XCTAssertEqual(state.registers.data[1], 0xffff8000);
+	XCTAssertEqual(state.registers.address[1], 0x4002);
 
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
@@ -502,8 +502,8 @@
 		0x4c91, 0x0206		// MOVEM.w (A1), A1/D1-D2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
-	state.data[2] = 0xffffffff;
+	state.registers.address[1] = 0x4000;
+	state.registers.data[2] = 0xffffffff;
 	*_machine->ram_at(0x4000) = 0x8000;
 	*_machine->ram_at(0x4002) = 0x2222;
 	*_machine->ram_at(0x4004) = 0x3333;
@@ -513,9 +513,9 @@
 
 	state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0xffff8000);
-	XCTAssertEqual(state.data[2], 0x00002222);
-	XCTAssertEqual(state.address[1], 0x3333);
+	XCTAssertEqual(state.registers.data[1], 0xffff8000);
+	XCTAssertEqual(state.registers.data[2], 0x00002222);
+	XCTAssertEqual(state.registers.address[1], 0x3333);
 
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
@@ -525,9 +525,9 @@
 		0x4891, 0x0206		// MOVEM.w A1/D1-D2, (A1)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
-	state.data[1] = 0x11111111;
-	state.data[2] = 0x22222222;
+	state.registers.address[1] = 0x4000;
+	state.registers.data[1] = 0x11111111;
+	state.registers.data[2] = 0x22222222;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -537,7 +537,7 @@
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x4002), 0x2222);
 	XCTAssertEqual(*_machine->ram_at(0x4004), 0x4000);
-	XCTAssertEqual(state.address[1], 0x4000);
+	XCTAssertEqual(state.registers.address[1], 0x4000);
 
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
@@ -549,15 +549,15 @@
 		0x1401		// MOVE.b D1, D2
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x00000078);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x00000078);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -569,8 +569,8 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x8090fea1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0x8090fea1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -579,15 +579,15 @@
 		0x34bc, 0x0000		// MOVE #$0, (A2)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
+	state.registers.address[2] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x1234;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
@@ -597,8 +597,8 @@
 		0x24da		// MOVE.l (A2)+, (A2)+
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.status = Flag::Negative;
+	state.registers.address[2] = 0x3000;
+	state.registers.status = ConditionCode::Negative;
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
@@ -606,8 +606,8 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3008);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.address[2], 0x3008);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xaaaa);
@@ -620,8 +620,8 @@
 		0x251a		// MOVE.l (A2)+, -(A2)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.status = Flag::Negative;
+	state.registers.address[2] = 0x3000;
+	state.registers.status = ConditionCode::Negative;
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
@@ -629,8 +629,8 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0);
@@ -643,9 +643,9 @@
 		0x25a2, 0x1004		// MOVE.L -(A2), 4(A2,D1)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3004;
-	state.data[1] = 0;
-	state.status = Flag::Negative;
+	state.registers.address[2] = 0x3004;
+	state.registers.data[1] = 0;
+	state.registers.status = ConditionCode::Negative;
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
@@ -653,9 +653,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xaaaa);
@@ -668,14 +668,14 @@
 		0x33c1, 0x0000, 0x3000		// MOVE.W D1, ($3000).L
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x5678;
+	state.registers.data[1] = 0x5678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x5678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x5678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -690,7 +690,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);	/* !! 8 !! */
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);	/* !! 8 !! */
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xeeee);
 	XCTAssertEqual(*_machine->ram_at(0x3006), 0xeeee);
 	XCTAssertEqual(36, _machine->get_cycle_count());
@@ -703,14 +703,14 @@
 		0x244a		// MOVEA.l A2, A2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
+	state.registers.address[2] = 0xffffffff;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -719,16 +719,16 @@
 		0x3442		// MOVEA.w D2, A2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
-	state.data[2] = 0x12345678;
+	state.registers.address[2] = 0xffffffff;
+	state.registers.data[2] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x00005678);
-	XCTAssertEqual(state.data[2], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0x00005678);
+	XCTAssertEqual(state.registers.data[2], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -737,16 +737,16 @@
 		0x3442		// MOVEA.w D2, A2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
-	state.data[2] = 0x12348756;
+	state.registers.address[2] = 0xffffffff;
+	state.registers.data[2] = 0x12348756;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xffff8756);
-	XCTAssertEqual(state.data[2], 0x12348756);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xffff8756);
+	XCTAssertEqual(state.registers.data[2], 0x12348756);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -755,14 +755,14 @@
 		0x247c, 0x0000, 0x0001		// MOVEA.L #$1, A2
 	});
 	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
+	state.registers.address[2] = 0xffffffff;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -773,7 +773,7 @@
 		0x030e, 0x0004		// MOVEP.w 4(A6), D1
 	});
 	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
+	state.registers.address[6] = 0x3000;
 	*_machine->ram_at(0x3004) = 0x1200;
 	*_machine->ram_at(0x3006) = 0x3400;
 
@@ -781,9 +781,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
-	XCTAssertEqual(state.data[1], 0x1234);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[6], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0x1234);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -792,7 +792,7 @@
 		0x034e, 0x0002		// MOVEP.l 2(A6), D1
 	});
 	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
+	state.registers.address[6] = 0x3000;
 	*_machine->ram_at(0x3002) = 0x1200;
 	*_machine->ram_at(0x3004) = 0x3400;
 	*_machine->ram_at(0x3006) = 0x5600;
@@ -802,9 +802,9 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[6], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -813,18 +813,18 @@
 		0x038e, 0x0002		// MOVEP.w D1, 2(A6)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
-	state.data[1] = 0x12345678;
+	state.registers.address[6] = 0x3000;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
+	XCTAssertEqual(state.registers.address[6], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x5600);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0x7800);
 
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -833,21 +833,21 @@
 		0x03ce, 0x0002		// MOVEP.l D1, 2(A6)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
-	state.data[1] = 0x12345678;
+	state.registers.address[6] = 0x3000;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
+	XCTAssertEqual(state.registers.address[6], 0x3000);
 
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x1200);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0x3400);
 	XCTAssertEqual(*_machine->ram_at(0x3006), 0x5600);
 	XCTAssertEqual(*_machine->ram_at(0x3008), 0x7800);
 
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -858,14 +858,14 @@
 		0x7201		// MOVEQ #1, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xffffffff;
+	state.registers.data[1] = 0xffffffff;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -874,15 +874,15 @@
 		0x72ff		// MOVEQ #-1, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
 
 	_machine->set_processor_state(state);
 
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -891,15 +891,15 @@
 		0x7280		// MOVEQ #$80, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[1] = 0x12345678;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffff80);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xffffff80);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -908,15 +908,15 @@
 		0x7200		// MOVEQ #00, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[1] = 0x12345678;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	state.registers.data[1] = 0x12345678;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -927,14 +927,14 @@
 		0x40c1		// MOVE SR, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.status = 0x271f;
+	state.registers.status = 0x271f;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x271f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.data[1], 0x271f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -945,13 +945,13 @@
 		0x44fc, 0x001f		// MOVE #$1f, CCR
 	});
 	auto state = _machine->get_processor_state();
-	state.status = 0;	// i.e. not even supervisor.
+	state.registers.status = 0;	// i.e. not even supervisor.
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0x1f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0x1f);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -962,15 +962,15 @@
 		0x46fc, 0x0700		// MOVE #$700, SR
 	});
 	auto state = _machine->get_processor_state();
-	state.supervisor_stack_pointer = 0x3000;
-	state.user_stack_pointer = 0;
+	state.registers.supervisor_stack_pointer = 0x3000;
+	state.registers.user_stack_pointer = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.stack_pointer(), 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -981,13 +981,13 @@
 		0x4e69		// MOVE USP, A1
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x12348756;
+	state.registers.address[1] = 0x12348756;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0);
+	XCTAssertEqual(state.registers.address[1], 0);
 }
 
 // MARK: PEA
@@ -997,15 +997,15 @@
 		0x4851		// PEA (A1)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000ffff;
+	state.registers.address[1] = 0x3000ffff;
 	_machine->set_initial_stack_pointer(0x1996);
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3000ffff);
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	XCTAssertEqual(state.registers.address[1], 0x3000ffff);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0xffff);
 	XCTAssertEqual(12, _machine->get_cycle_count());
@@ -1020,7 +1020,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x100e);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x100e);
 	XCTAssertEqual(*_machine->ram_at(0x1010), 0x1012);
 	XCTAssertEqual(*_machine->ram_at(0x1008), 0x0000);
 	XCTAssertEqual(12, _machine->get_cycle_count());
@@ -1035,7 +1035,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x100e);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x100e);
 	XCTAssertEqual(*_machine->ram_at(0x1010), 0x1016);
 	XCTAssertEqual(*_machine->ram_at(0x1008), 0x0000);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -1050,7 +1050,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0x3000);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -1065,7 +1065,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0x5678);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -1078,15 +1078,15 @@
 		0x51c0		// SF D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::Extend;
+	state.registers.data[0] = 0x12345678;
+	state.registers.status = ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSTDn {
@@ -1094,15 +1094,15 @@
 		0x50c0		// ST D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::Extend;
+	state.registers.data[0] = 0x12345678;
+	state.registers.status = ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSLSDn {
@@ -1110,15 +1110,15 @@
 		0x53c0		// SLS D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0x12345678;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testSGTAnXTrue {
@@ -1126,16 +1126,16 @@
 		0x5ee8, 0x0002		// SGT 2(a0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
+	state.registers.address[0] = 0x3000;
 	*_machine->ram_at(0x3002) = 0x8800;
-	state.status = Flag::Extend;
+	state.registers.status = ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xff00);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSGTAnXFalse {
@@ -1143,16 +1143,16 @@
 		0x5ee8, 0x0002		// SGT 2(a0)
 	});
 	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
+	state.registers.address[0] = 0x3000;
 	*_machine->ram_at(0x3002) = 0x8800;
-	state.status = Flag::ConditionCodes;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 
@@ -1163,14 +1163,14 @@
 		0x4841		// SWAP D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12348756;
+	state.registers.data[1] = 0x12348756;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x87561234);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x87561234);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 // MARK: TST
@@ -1180,15 +1180,15 @@
 		0x4a44		// TST.w D4
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[4] = 0xfff1;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	state.registers.data[4] = 0xfff1;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend);
-	XCTAssertEqual(state.data[4], 0xfff1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[4], 0xfff1);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1197,15 +1197,15 @@
 		0x4a84		// TST.l D4
 	});
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[4] = 0;
+	state.registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	state.registers.data[4] = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero | Flag::Extend);
-	XCTAssertEqual(state.data[4], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[4], 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1219,7 +1219,7 @@
 	});
 
 	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
+	state.registers.address[6] = 0x3000;
 	*_machine->ram_at(0x3000) = 0x0000;
 	*_machine->ram_at(0x3002) = 0x4000;
 
@@ -1227,8 +1227,8 @@
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x4000);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x3004);
+	XCTAssertEqual(state.registers.address[6], 0x4000);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x3004);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -1243,7 +1243,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x4000);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x4000);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm b/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm
index 24b85da5b..9e0b9c609 100644
--- a/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm	
@@ -34,16 +34,16 @@
 		0xe521		// ASL.B D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd59c);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -52,16 +52,16 @@
 		0xe521		// ASL.B D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 105;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 105;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 105);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 105);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -70,16 +70,16 @@
 		0xe561		// ASL.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -88,16 +88,16 @@
 		0xe561		// ASL.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0xb;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d3800);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Overflow | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3d3800);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -106,16 +106,16 @@
 		0xe5a1		// ASL.l D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Overflow | Flag::Carry | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -124,15 +124,15 @@
 		0xe181		// ASL.l #8, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x3dd56700);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x3dd56700);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -146,7 +146,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1998);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -162,7 +162,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x8af0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0782);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -173,16 +173,16 @@
 		0xe421		// ASR.B D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd519);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd519);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -191,16 +191,16 @@
 		0xe421		// ASR.B D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 105;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 105;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 105);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 105);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -209,16 +209,16 @@
 		0xe461		// ASR.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -227,16 +227,16 @@
 		0xe461		// ASR.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0xb;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dfffa);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3dfffa);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -245,16 +245,16 @@
 		0xe4a1		// ASR.l D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffffff);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xffffffff);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -263,15 +263,15 @@
 		0xe081		// ASR.l #8, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffce3dd5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xffce3dd5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -285,7 +285,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xc666);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -301,7 +301,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xc2bc);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0782);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -312,16 +312,16 @@
 		0xe529		// LSL.b D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd59c);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -330,16 +330,16 @@
 		0xe529		// LSL.b D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x69;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x69;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 0x69);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 0x69);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -348,16 +348,16 @@
 		0xe569		// LSL.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -366,16 +366,16 @@
 		0xe569		// LSL.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0xb;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d3800);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3d3800);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -384,16 +384,16 @@
 		0xe5a9		// LSL.l D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -402,14 +402,14 @@
 		0xe189		// LSL.l #8, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
+	state.registers.data[1] = 0xce3dd567;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x3dd56700);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x3dd56700);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -423,7 +423,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1998);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -434,16 +434,16 @@
 		0xe429		// LSR.b D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 2;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd519);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd519);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -452,16 +452,16 @@
 		0xe429		// LSR.b D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x69;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x69;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 0x69);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 0x69);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -470,16 +470,16 @@
 		0xe469		// LSR.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -488,16 +488,16 @@
 		0xe469		// LSR.w D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0xb;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d001a);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[1], 0xce3d001a);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -506,16 +506,16 @@
 		0xe4a9		// LSR.l D2, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
+	state.registers.data[1] = 0xce3dd567;
+	state.registers.data[2] = 0x20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -524,14 +524,14 @@
 		0xe089		// LSR.L #8, D1
 	});
 	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
+	state.registers.data[1] = 0xce3dd567;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0xce3dd5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -545,7 +545,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x4666);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -556,14 +556,14 @@
 		0xe118		// ROL.B #8, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
+	state.registers.data[0] = 0xce3dd567;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -572,14 +572,14 @@
 		0xe318		// ROL.B #1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
+	state.registers.data[0] = 0xce3dd567;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5ce);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5ce);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -588,15 +588,15 @@
 		0xe518		// ROL.B #2, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd59d);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd59d);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -605,15 +605,15 @@
 		0xef18		// ROL.B #7, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5b3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5b3);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -622,15 +622,15 @@
 		0xe158		// ROL.w #7, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d67d5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d67d5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -639,15 +639,15 @@
 		0xe798		// ROL.l #3, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x71eeab3e);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x71eeab3e);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -656,9 +656,9 @@
 		0xe378		// ROL.l D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = d1;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -667,27 +667,27 @@
 - (void)testROLw_D1D0_20 {
 	[self performROLw_D1D0d1:20];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d567d);
-	XCTAssertEqual(state.data[1], 20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d567d);
+	XCTAssertEqual(state.registers.data[1], 20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(46, _machine->get_cycle_count());
 }
 
 - (void)testROLw_D1D0_36 {
 	[self performROLw_D1D0d1:36];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d567d);
-	XCTAssertEqual(state.data[1], 36);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d567d);
+	XCTAssertEqual(state.registers.data[1], 36);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(78, _machine->get_cycle_count());
 }
 
 - (void)testROLw_D1D0_0 {
 	[self performROLw_D1D0d1:0];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -696,17 +696,17 @@
 		0xe3b8		// ROL.l D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 200;
-	state.status = Flag::ConditionCodes;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = 200;
+	state.registers.status = ConditionCode::AllConditions;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x3dd567ce);
-	XCTAssertEqual(state.data[1], 200);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x3dd567ce);
+	XCTAssertEqual(state.registers.data[1], 200);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -726,7 +726,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaacf);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 }
 
 - (void)testROLm_0 {
@@ -734,7 +734,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 // MARK: ROR
@@ -745,7 +745,7 @@
 		uint16_t(0xe018 | (immediate << 9))		// ROR.b #, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
+	state.registers.data[0] = 0xce3dd599;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
@@ -755,8 +755,8 @@
 	[self performRORbIMM:8];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -764,8 +764,8 @@
 	[self performRORbIMM:1];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5cc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5cc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -773,8 +773,8 @@
 	[self performRORbIMM:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -782,8 +782,8 @@
 	[self performRORbIMM:7];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd533);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd533);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -792,14 +792,14 @@
 		0xec58		// ROR.w #6, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
+	state.registers.data[0] = 0xce3dd599;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d6756);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3d6756);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -808,14 +808,14 @@
 		0xea98		// ROR.l #5, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
+	state.registers.data[0] = 0xce3dd599;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce71eeac);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce71eeac);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -824,16 +824,16 @@
 		0xe238		// ROR.b D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-	state.data[1] = 20;
+	state.registers.data[0] = 0xce3dd599;
+	state.registers.data[1] = 20;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.data[1], 20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.data[1], 20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(46, _machine->get_cycle_count());
 }
 
@@ -842,16 +842,16 @@
 		0xe2b8		// ROR.l D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-	state.data[1] = 26;
+	state.registers.data[0] = 0xce3dd599;
+	state.registers.data[1] = 26;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x8f756673);
-	XCTAssertEqual(state.data[1], 26);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x8f756673);
+	XCTAssertEqual(state.registers.data[1], 26);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(60, _machine->get_cycle_count());
 }
 
@@ -871,7 +871,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 }
 
 - (void)testRORm_d560 {
@@ -879,7 +879,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x6ab0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 // MARK: ROXL
@@ -889,31 +889,31 @@
 		0xe330		// ROXL.b D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 9;
-	state.status |= ccr;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = 9;
+	state.registers.status |= ccr;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(24, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 9);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 9);
 }
 
 - (void)testROXLb_extend {
-	[self performROXLb_Dnccr:Flag::ConditionCodes];
+	[self performROXLb_Dnccr:ConditionCode::AllConditions];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testROXLb {
 	[self performROXLb_Dnccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performROXLw_Dnd1:(uint32_t)d1 ccr:(uint16_t)ccr {
@@ -921,41 +921,41 @@
 		0xe370		// ROXL.w D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status |= ccr;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = d1;
+	state.registers.status |= ccr;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testROXLw_17 {
-	[self performROXLw_Dnd1:17 ccr:Flag::Carry];
+	[self performROXLw_Dnd1:17 ccr:ConditionCode::Carry];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(40, _machine->get_cycle_count());
 }
 
 - (void)testROXLw_5 {
-	[self performROXLw_Dnd1:5 ccr:Flag::Extend];
+	[self performROXLw_Dnd1:5 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dacfd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dacfd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
 - (void)testROXLw_22 {
-	[self performROXLw_Dnd1:22 ccr:Flag::Extend];
+	[self performROXLw_Dnd1:22 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dacfd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dacfd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(50, _machine->get_cycle_count());
 }
 
@@ -964,16 +964,16 @@
 		0xe3b0		// ROXL.l D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 33;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = 33;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(74, _machine->get_cycle_count());
 }
 
@@ -982,15 +982,15 @@
 		0xe950		// ROXL.w #4, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3d3600;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = 0xce3d3600;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d6009);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d6009);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -1004,7 +1004,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaace);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -1015,31 +1015,31 @@
 		0xe230		// ROXR.b D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 9;
-	state.status |= ccr;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = 9;
+	state.registers.status |= ccr;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(24, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 9);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 9);
 }
 
 - (void)testROXRb_extend {
-	[self performROXRb_Dnccr:Flag::ConditionCodes];
+	[self performROXRb_Dnccr:ConditionCode::AllConditions];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testROXRb {
 	[self performROXRb_Dnccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performROXRw_Dnd1:(uint32_t)d1 ccr:(uint16_t)ccr {
@@ -1047,41 +1047,41 @@
 		0xe270		// ROXR.w D1, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status |= ccr;
+	state.registers.data[0] = 0xce3dd567;
+	state.registers.data[1] = d1;
+	state.registers.status |= ccr;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testROXRw_17 {
-	[self performROXRw_Dnd1:17 ccr:Flag::Carry];
+	[self performROXRw_Dnd1:17 ccr:ConditionCode::Carry];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(40, _machine->get_cycle_count());
 }
 
 - (void)testROXRw_5 {
-	[self performROXRw_Dnd1:5 ccr:Flag::Extend];
+	[self performROXRw_Dnd1:5 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d7eab);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3d7eab);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
 - (void)testROXRw_22 {
-	[self performROXRw_Dnd1:22 ccr:Flag::Extend];
+	[self performROXRw_Dnd1:22 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d7eab);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3d7eab);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(50, _machine->get_cycle_count());
 }
 
@@ -1090,15 +1090,15 @@
 		0xe890		// ROXR.L #4, D0
 	});
 	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3d3600;
-	state.status |= Flag::Extend;
+	state.registers.data[0] = 0xce3d3600;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1ce3d360);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x1ce3d360);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -1108,14 +1108,14 @@
 	});
 	*_machine->ram_at(0x3000) = 0xd567;
 	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend;
+	state.registers.status |= ConditionCode::Extend;
 
 	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
 	state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000Tests.mm b/OSBindings/Mac/Clock SignalTests/68000Tests.mm
index dc524b328..18cbe8e51 100644
--- a/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
@@ -12,6 +12,7 @@
 
 #include "TestRunner68000.hpp"
 
+/*
 class CPU::MC68000::ProcessorStorageTests {
 	public:
 		ProcessorStorageTests(const CPU::MC68000::ProcessorStorage &storage, const char *coverage_file_name) {
@@ -80,6 +81,7 @@ class CPU::MC68000::ProcessorStorageTests {
 		NSMutableSet<NSNumber *> *false_invalids_;
 		NSMutableSet<NSNumber *> *false_valids_;
 };
+*/
 
 @interface NSSet (CSHexDump)
 
@@ -126,7 +128,7 @@ class CPU::MC68000::ProcessorStorageTests {
 
 		auto state = _machine->get_processor_state();
 		const uint8_t bcd_d = ((d / 10) * 16) + (d % 10);
-		state.data[0] = bcd_d;
+		state.registers.data[0] = bcd_d;
 		_machine->set_processor_state(state);
 
 		_machine->run_for_instructions(1);
@@ -134,7 +136,7 @@ class CPU::MC68000::ProcessorStorageTests {
 		state = _machine->get_processor_state();
 		const uint8_t double_d = (d * 2) % 100;
 		const uint8_t bcd_double_d = ((double_d / 10) * 16) + (double_d % 10);
-		XCTAssert(state.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.data[0], bcd_double_d);
+		XCTAssert(state.registers.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.registers.data[0], bcd_double_d);
 	}
 }
 
@@ -152,9 +154,9 @@ class CPU::MC68000::ProcessorStorageTests {
 	_machine->run_for_instructions(4);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssert(state.supervisor_stack_pointer == 0x1000 - 6, @"Exception information should have been pushed to stack.");
+	XCTAssert(state.registers.supervisor_stack_pointer == 0x1000 - 6, @"Exception information should have been pushed to stack.");
 
-	const uint16_t *const stack_top = _machine->ram_at(state.supervisor_stack_pointer);
+	const uint16_t *const stack_top = _machine->ram_at(state.registers.supervisor_stack_pointer);
 	XCTAssert(stack_top[1] == 0x0000 && stack_top[2] == 0x1006, @"Return address should point to instruction after DIVU.");
 }
 
@@ -177,28 +179,28 @@ class CPU::MC68000::ProcessorStorageTests {
 	// Perform MOVE #fb2e, D0
 	_machine->run_for_instructions(1);
 	auto state = _machine->get_processor_state();
-	XCTAssert(state.data[0] == 0xfb2e);
+	XCTAssert(state.registers.data[0] == 0xfb2e);
 
 	// Perform MOVE D0, D1
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.data[1] == 0xfb2e);
+	XCTAssert(state.registers.data[1] == 0xfb2e);
 
 	// Perform MOVEA D0, A0
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.address[0]);
+	XCTAssert(state.registers.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.registers.address[0]);
 
 	// Perform MOVEA.w (0x1000), A1
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.address[1]);
+	XCTAssert(state.registers.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.registers.address[1]);
 
 	// Perform MOVE #$400, A4; MOVE.l (A4), D2
 	_machine->run_for_instructions(2);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[4] == 0x1000, "A4 was %08x instead of 0x00001000", state.address[4]);
-	XCTAssert(state.data[2] == 0x303cfb2e, "D2 was %08x instead of 0x303cfb2e", state.data[2]);
+	XCTAssert(state.registers.address[4] == 0x1000, "A4 was %08x instead of 0x00001000", state.registers.address[4]);
+	XCTAssert(state.registers.data[2] == 0x303cfb2e, "D2 was %08x instead of 0x303cfb2e", state.registers.data[2]);
 }
 
 - (void)testVectoredInterrupt {
@@ -223,7 +225,7 @@ class CPU::MC68000::ProcessorStorageTests {
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->processor().get_state();
-	XCTAssertEqual(state.program_counter, 0x1008);	// i.e. the interrupt happened, the instruction performed was the one at 1004, and therefore
+	XCTAssertEqual(state.registers.program_counter, 0x1008);	// i.e. the interrupt happened, the instruction performed was the one at 1004, and therefore
 													// by the wonders of prefetch the program counter is now at 1008.
 }
 
@@ -287,7 +289,7 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssertEqual(_machine->get_cycle_count(), 6 + 2);
 }
 
-- (void)testOpcodeCoverage {
+/*- (void)testOpcodeCoverage {
 	// Perform an audit of implemented instructions.
 	CPU::MC68000::ProcessorStorageTests storage_tests(
 		_machine->processor(),
@@ -479,6 +481,6 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssert(!trimmedInvalids.count, "%@ opcodes should be valid but aren't: %@", @(trimmedInvalids.count), trimmedInvalids.hexDump);
 
 //	XCTAssert(!falseInvalids.count, "%@ opcodes should be valid but aren't: %@", @(falseInvalids.count), falseInvalids.hexDump);
-}
+}*/
 
 @end
diff --git a/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp b/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp
index 061f1a0c8..414da9395 100644
--- a/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp	
+++ b/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp	
@@ -10,17 +10,18 @@
 #define TestRunner68000_h
 
 #include <array>
+#include <vector>
 
-#include "../../../Processors/68000/68000.hpp"
+#include "../../../Processors/68000Mk2/68000Mk2.hpp"
 
-using Flag = CPU::MC68000::Flag;
+using namespace InstructionSet::M68k;
 
 /*!
 	Provides a 68000 with 64kb of RAM in its low address space;
 	/RESET will put the supervisor stack pointer at 0xFFFF and
 	begin execution at 0x0400.
 */
-class RAM68000: public CPU::MC68000::BusHandler {
+class RAM68000: public CPU::MC68000Mk2::BusHandler {
 	public:
 		RAM68000() : m68000_(*this) {
 			// Setup the /RESET vector.
@@ -31,7 +32,7 @@ class RAM68000: public CPU::MC68000::BusHandler {
 
 			// Ensure the condition codes start unset.
 			auto state = get_processor_state();
-			state.status &= ~Flag::ConditionCodes;
+			state.registers.status &= ~ConditionCode::AllConditions;
 			set_processor_state(state);
 		}
 
@@ -84,30 +85,30 @@ class RAM68000: public CPU::MC68000::BusHandler {
 			return &ram_[(address >> 1) % ram_.size()];
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t word_address = cycle.word_address();
 			if(instructions_remaining_) duration_ += cycle.length;
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				if(cycle.operation & Microcycle::InterruptAcknowledge) {
-					cycle.value->halves.low = 10;
+					cycle.value->b = 10;
 				} else {
 					switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
 						default: break;
 
 						case Microcycle::SelectWord | Microcycle::Read:
-							cycle.value->full = ram_[word_address % ram_.size()];
+							cycle.value->w = ram_[word_address % ram_.size()];
 						break;
 						case Microcycle::SelectByte | Microcycle::Read:
-							cycle.value->halves.low = ram_[word_address % ram_.size()] >> cycle.byte_shift();
+							cycle.value->b = ram_[word_address % ram_.size()] >> cycle.byte_shift();
 						break;
 						case Microcycle::SelectWord:
-							ram_[word_address % ram_.size()] = cycle.value->full;
+							ram_[word_address % ram_.size()] = cycle.value->w;
 						break;
 						case Microcycle::SelectByte:
 							ram_[word_address % ram_.size()] = uint16_t(
-								(cycle.value->halves.low << cycle.byte_shift()) |
+								(cycle.value->b << cycle.byte_shift()) |
 								(ram_[word_address % ram_.size()] & cycle.untouched_byte_mask())
 							);
 						break;
@@ -118,15 +119,15 @@ class RAM68000: public CPU::MC68000::BusHandler {
 			return HalfCycles(0);
 		}
 
-		CPU::MC68000::Processor<RAM68000, true>::State get_processor_state() {
+		CPU::MC68000Mk2::State get_processor_state() {
 			return m68000_.get_state();
 		}
 
-		void set_processor_state(const CPU::MC68000::Processor<RAM68000, true>::State &state) {
+		void set_processor_state(const CPU::MC68000Mk2::State &state) {
 			m68000_.set_state(state);
 		}
 
-		CPU::MC68000::Processor<RAM68000, true, true> &processor() {
+		auto &processor() {
 			return m68000_;
 		}
 
@@ -139,7 +140,7 @@ class RAM68000: public CPU::MC68000::BusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<RAM68000, true, true> m68000_;
+		CPU::MC68000Mk2::Processor<RAM68000, true, false, true> m68000_;
 		std::array<uint16_t, 256*1024> ram_{};
 		int instructions_remaining_;
 		HalfCycles duration_;

From 2c6b9b4c9da240d001864ac938fa4fda01b0007e Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 11:32:00 -0400
Subject: [PATCH 2/6] Switch comparative trace tests to 68000 Mk2.

---
 .../Clock SignalTests/68000ArithmeticTests.mm  |  1 +
 .../Mac/Clock SignalTests/Comparative68000.hpp | 10 +++++-----
 .../Mac/Clock SignalTests/EmuTOSTests.mm       | 18 +++++++++---------
 OSBindings/Mac/Clock SignalTests/QLTests.mm    | 16 ++++++++--------
 4 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
index 625e94030..d6ebc8d67 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
@@ -225,6 +225,7 @@
 	});
 	auto state = self.machine->get_processor_state();
 	state.registers.status = ConditionCode::AllConditions;
+	state.registers.address[2] = 0;
 
 	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
diff --git a/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp b/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp
index 6c8c5472d..b85e97248 100644
--- a/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp	
+++ b/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp	
@@ -11,9 +11,9 @@
 
 #include <zlib.h>
 
-#include "68000.hpp"
+#include "68000Mk2.hpp"
 
-class ComparativeBusHandler: public CPU::MC68000::BusHandler {
+class ComparativeBusHandler: public CPU::MC68000Mk2::BusHandler {
 	public:
 		ComparativeBusHandler(const char *trace_name) {
 			trace = gzopen(trace_name, "rt");
@@ -30,14 +30,14 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
 			++line_count;
 
 			// Generate state locally.
-			const auto state = get_state();
+			const auto state = get_state().registers;
 			char local_state[300];
 			sprintf(local_state, "%04x: %02x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
 				address,
 				state.status,
 				state.data[0], state.data[1], state.data[2], state.data[3], state.data[4], state.data[5], state.data[6], state.data[7],
 				state.address[0], state.address[1], state.address[2], state.address[3], state.address[4], state.address[5], state.address[6],
-				(state.status & 0x2000) ? state.supervisor_stack_pointer : state.user_stack_pointer
+				state.stack_pointer()
 				);
 
 			// Check that the two coincide.
@@ -49,7 +49,7 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
 			}
 		}
 
-		virtual CPU::MC68000::ProcessorState get_state() = 0;
+		virtual CPU::MC68000Mk2::State get_state() = 0;
 
 	private:
 		int line_count = 0;
diff --git a/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm b/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
index 978d6387e..2ac49ef95 100644
--- a/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm	
@@ -13,7 +13,7 @@
 
 //#define LOG_TRACE
 
-#include "68000.hpp"
+#include "68000Mk2.hpp"
 #include "Comparative68000.hpp"
 #include "CSROMFetcher.hpp"
 
@@ -32,11 +32,11 @@ class EmuTOS: public ComparativeBusHandler {
 			m68000_.run_for(cycles);
 		}
 
-		CPU::MC68000::ProcessorState get_state() final {
+		CPU::MC68000Mk2::State get_state() final {
 			return m68000_.get_state();
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t address = cycle.word_address();
 			uint32_t word_address = address;
 
@@ -56,7 +56,7 @@ class EmuTOS: public ComparativeBusHandler {
 				word_address %= ram_.size();
 			}
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				uint16_t peripheral_result = 0xffff;
 				if(is_peripheral) {
@@ -72,16 +72,16 @@ class EmuTOS: public ComparativeBusHandler {
 					default: break;
 
 					case Microcycle::SelectWord | Microcycle::Read:
-						cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
+						cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
 					break;
 					case Microcycle::SelectByte | Microcycle::Read:
-						cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
+						cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
 					break;
 					case Microcycle::SelectWord:
-						base[word_address] = cycle.value->full;
+						base[word_address] = cycle.value->w;
 					break;
 					case Microcycle::SelectByte:
-						base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
+						base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
 					break;
 				}
 			}
@@ -90,7 +90,7 @@ class EmuTOS: public ComparativeBusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<EmuTOS, true, true> m68000_;
+		CPU::MC68000Mk2::Processor<EmuTOS, true, true> m68000_;
 
 		std::vector<uint16_t> emuTOS_;
 		std::array<uint16_t, 256*1024> ram_;
diff --git a/OSBindings/Mac/Clock SignalTests/QLTests.mm b/OSBindings/Mac/Clock SignalTests/QLTests.mm
index 79f32f10c..d7d124d0c 100644
--- a/OSBindings/Mac/Clock SignalTests/QLTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/QLTests.mm	
@@ -35,11 +35,11 @@ class QL: public ComparativeBusHandler {
 			m68000_.run_for(cycles);
 		}
 
-		CPU::MC68000::ProcessorState get_state() final {
+		CPU::MC68000Mk2::State get_state() final {
 			return m68000_.get_state();
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t address = cycle.word_address();
 			uint32_t word_address = address;
 
@@ -56,7 +56,7 @@ class QL: public ComparativeBusHandler {
 				word_address %= ram_.size();
 			}
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				uint16_t peripheral_result = 0xffff;
 
@@ -64,18 +64,18 @@ class QL: public ComparativeBusHandler {
 					default: break;
 
 					case Microcycle::SelectWord | Microcycle::Read:
-						cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
+						cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
 					break;
 					case Microcycle::SelectByte | Microcycle::Read:
-						cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
+						cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
 					break;
 					case Microcycle::SelectWord:
 						assert(!(is_rom && !is_peripheral));
-						if(!is_peripheral) base[word_address] = cycle.value->full;
+						if(!is_peripheral) base[word_address] = cycle.value->w;
 					break;
 					case Microcycle::SelectByte:
 						assert(!(is_rom && !is_peripheral));
-						if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
+						if(!is_peripheral) base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
 					break;
 				}
 			}
@@ -84,7 +84,7 @@ class QL: public ComparativeBusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<QL, true, true> m68000_;
+		CPU::MC68000Mk2::Processor<QL, true, false, true> m68000_;
 
 		std::vector<uint16_t> rom_;
 		std::array<uint16_t, 64*1024> ram_;

From 9709b9b1b16847487dbcce1c88bbebf28da8f0ff Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 11:37:39 -0400
Subject: [PATCH 3/6] Standard exceptions don't raise the interrupt level.

---
 Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 1fdf0c692..418c39aca 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -381,7 +381,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			// Switch to supervisor mode, disable interrupts.
 			status_.is_supervisor = true;
 			status_.trace_flag = 0;
-			status_.interrupt_level = 7;
 			should_trace_ = 0;
 			did_update_status();
 

From 5db6a937cb438b0ba8e8b197fca684c1e36a527e Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 11:47:21 -0400
Subject: [PATCH 4/6] Have TRAP and TRAPV push the next instruction address to
 the stack.

---
 Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 418c39aca..277737e7d 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -2425,6 +2425,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 		// or that of the instruction after?
 		BeginState(TRAP):
 			IdleBus(2);
+			instruction_address_.l += 2;	// Push the address of the instruction after the trap.
 			exception_vector_ = (opcode_ & 15) + InstructionSet::M68k::Exception::TrapBase;
 		MoveToStateSpecific(StandardException);
 
@@ -2433,6 +2434,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			if(!status_.overflow_flag) {
 				MoveToStateSpecific(Decode);
 			}
+			instruction_address_.l += 2;	// Push the address of the instruction after the trap.
 			exception_vector_ = InstructionSet::M68k::Exception::TRAPV;
 		MoveToStateSpecific(StandardException);
 

From a5f2dfbc0cc4a3915f7193e326068599ee72fbdf Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 11:47:42 -0400
Subject: [PATCH 5/6] Initialise registers to 0 for better testability.

TODO: is this the real initial state?
---
 Processors/68000Mk2/Implementation/68000Mk2Storage.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
index 2113dfd53..be3bb8c8c 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
@@ -46,7 +46,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
 	// Register state.
 	InstructionSet::M68k::Status status_;
 	SlicedInt32 program_counter_;
-	SlicedInt32 registers_[16];		// D0–D7 followed by A0–A7.
+	SlicedInt32 registers_[16]{};		// D0–D7 followed by A0–A7.
 	SlicedInt32 stack_pointers_[2];
 
 	/// Current state of the DTACK input.

From 72425fc2e1ffa77542e6f25537a31496e76f22bc Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 25 May 2022 13:00:36 -0400
Subject: [PATCH 6/6] Fix bus data size of MOVE.b xx, -(An).

---
 Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 277737e7d..4db2a457e 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -1630,7 +1630,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				break;
 			}
 
-			SetupDataAccess(0, Microcycle::SelectWord);
 			SetDataAddress(registers_[8 + instruction_.reg(1)].l);
 			Access(operand_[1].low);
 		MoveToStateSpecific(Decode);