From b9dbb6bcf87dc6535d2ab423ffcfdf5dac40936c Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 12 Jun 2017 18:55:04 -0400 Subject: [PATCH] Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate. --- Machines/ZX8081/Video.cpp | 2 +- Processors/Z80/Z80.hpp | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Machines/ZX8081/Video.cpp b/Machines/ZX8081/Video.cpp index 51e352bd5..5102cdffd 100644 --- a/Machines/ZX8081/Video.cpp +++ b/Machines/ZX8081/Video.cpp @@ -11,7 +11,7 @@ using namespace ZX8081; Video::Video() : - crt_(new Outputs::CRT::CRT(206 * 2, 1, Outputs::CRT::DisplayType::PAL50, 1)), + crt_(new Outputs::CRT::CRT(207 * 2, 1, Outputs::CRT::DisplayType::PAL50, 1)), line_data_(nullptr), line_data_pointer_(nullptr), cycles_since_update_(0), diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp index 244ca1807..04cdbc65a 100644 --- a/Processors/Z80/Z80.hpp +++ b/Processors/Z80/Z80.hpp @@ -385,19 +385,19 @@ template class Processor { /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.high), /* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ Program(FETCH16(temp16_, pc_), STORE16L(bc_, temp16_)), /* 0x44 NEG */ Program({MicroOp::NEG}), /* 0x45 RETN */ Program(POP(pc_), {MicroOp::RETN}), - /* 0x46 IM 0 */ Program({MicroOp::IM}), /* 0x47 LD I, A */ LD(i_, a_), + /* 0x46 IM 0 */ Program({MicroOp::IM}), /* 0x47 LD I, A */ Program(WAIT(1), {MicroOp::Move8, &a_, &i_}), /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.low), /* 0x4a ADC HL, BC */ ADC16(hl_, bc_), /* 0x4b LD BC, (nn) */ Program(FETCH16(temp16_, pc_), FETCH16L(bc_, temp16_)), /* 0x4c NEG */ Program({MicroOp::NEG}), /* 0x4d RETI */ Program(POP(pc_), {MicroOp::RETN}), - /* 0x4e IM 0/1 */ Program({MicroOp::IM}), /* 0x4f LD R, A */ LD(r_, a_), + /* 0x4e IM 0/1 */ Program({MicroOp::IM}), /* 0x4f LD R, A */ Program(WAIT(1), {MicroOp::Move8, &a_, &r_}), /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.high), /* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ Program(FETCH16(temp16_, pc_), STORE16L(de_, temp16_)), /* 0x54 NEG */ Program({MicroOp::NEG}), /* 0x55 RETN */ Program(POP(pc_), {MicroOp::RETN}), - /* 0x56 IM 1 */ Program({MicroOp::IM}), /* 0x57 LD A, I */ Program({MicroOp::Move8, &i_, &a_}, {MicroOp::SetAFlags}), + /* 0x56 IM 1 */ Program({MicroOp::IM}), /* 0x57 LD A, I */ Program(WAIT(1), {MicroOp::Move8, &i_, &a_}, {MicroOp::SetAFlags}), /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.low), /* 0x5a ADC HL, DE */ ADC16(hl_, de_), /* 0x5b LD DE, (nn) */ Program(FETCH16(temp16_, pc_), FETCH16L(de_, temp16_)), /* 0x5c NEG */ Program({MicroOp::NEG}), /* 0x5d RETN */ Program(POP(pc_), {MicroOp::RETN}), - /* 0x5e IM 2 */ Program({MicroOp::IM}), /* 0x5f LD A, R */ Program({MicroOp::Move8, &r_, &a_}, {MicroOp::SetAFlags}), + /* 0x5e IM 2 */ Program({MicroOp::IM}), /* 0x5f LD A, R */ Program(WAIT(1), {MicroOp::Move8, &r_, &a_}, {MicroOp::SetAFlags}), /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.high), /* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ Program(FETCH16(temp16_, pc_), STORE16L(hl_, temp16_)), /* 0x64 NEG */ Program({MicroOp::NEG}), /* 0x65 RETN */ Program(POP(pc_), {MicroOp::RETN}),