From ba15371948a4410c3f66092e5bd2c6af0258c890 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Mon, 19 Jun 2017 19:47:00 -0400
Subject: [PATCH] Introduced timing tests for LDI[R] and CPI[R], fixing a
 latent issue in the rejig of LD BC, nn while I'm here.

---
 .../Z80MachineCycleTests.swift                | 88 +++++++++++++++++++
 Processors/Z80/Z80.hpp                        |  2 +-
 2 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift b/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift
index a0ded5457..ad7b63f9a 100644
--- a/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift	
+++ b/OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift	
@@ -468,4 +468,92 @@ class Z80MachineCycleTests: XCTestCase {
 			]
 		)
 	}
+
+	// LDI
+	func testLDI() {
+		test(
+			program: [0xed, 0xa0],
+			busCycles: [
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .write, length: 5),
+			]
+		)
+	}
+
+	// CPI (NB: I've diverted from the documentation by assuming the five-cycle 'write' is an internal operation)
+	func testCPI() {
+		test(
+			program: [0xed, 0xa1],
+			busCycles: [
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .internalOperation, length: 5),
+			]
+		)
+	}
+
+	// LDIR
+	func testLDIR() {
+		test(
+			program: [
+				0x01, 0x02, 0x00,	// LD BC, 2
+				0xed, 0xb0,			// LDIR
+				0x00, 0x00, 0x00	// NOP, NOP, NOP
+			],
+			busCycles: [
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .read, length: 3),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .write, length: 5),
+				MachineCycle(operation: .internalOperation, length: 5),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .write, length: 5),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+			]
+		)
+	}
+
+	// CPIR (as per CPI; assumed no writes)
+	func testCPIR() {
+		test(
+			program: [
+				0x01, 0x02, 0x00,	// LD BC, 2
+				0xed, 0xb1,			// CPIR
+				0x00, 0x00, 0x00	// NOP, NOP, NOP
+			],
+			busCycles: [
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .read, length: 3),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .internalOperation, length: 5),
+				MachineCycle(operation: .internalOperation, length: 5),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .read, length: 3),
+				MachineCycle(operation: .internalOperation, length: 5),
+
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+				MachineCycle(operation: .readOpcode, length: 4),
+			]
+		)
+	}
 }
diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp
index 1b33c238f..ce940216e 100644
--- a/Processors/Z80/Z80.hpp
+++ b/Processors/Z80/Z80.hpp
@@ -534,7 +534,7 @@ template <class T> class Processor {
 				Instr(4, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r)
 
 			InstructionTable base_program_table = {
-				/* 0x00 NOP */			NOP,								/* 0x01 LD BC, nn */	StdInstr(Read16(pc_, bc_)),
+				/* 0x00 NOP */			NOP,								/* 0x01 LD BC, nn */	StdInstr(Read16Inc(pc_, bc_)),
 				/* 0x02 LD (BC), A */	StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)),
 
 				/* 0x03 INC BC;	0x04 INC B;	0x05 DEC B;	0x06 LD B, n */