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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.

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This commit is contained in:
Thomas Harte 2017-06-19 19:47:00 -04:00
parent 73dbaebbc1
commit ba15371948
2 changed files with 89 additions and 1 deletions
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88
OSBindings/Mac/Clock SignalTests/Z80MachineCycleTests.swift
View File

@ -468,4 +468,92 @@ class Z80MachineCycleTests: XCTestCase {
] ]
) )
} }
// LDI
func testLDI() {
test(
program: [0xed, 0xa0],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .write, length: 5),
]
)
}
// CPI (NB: I've diverted from the documentation by assuming the five-cycle 'write' is an internal operation)
func testCPI() {
test(
program: [0xed, 0xa1],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .internalOperation, length: 5),
]
)
}
// LDIR
func testLDIR() {
test(
program: [
0x01, 0x02, 0x00, // LD BC, 2
0xed, 0xb0, // LDIR
0x00, 0x00, 0x00 // NOP, NOP, NOP
],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .write, length: 5),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .write, length: 5),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
]
)
}
// CPIR (as per CPI; assumed no writes)
func testCPIR() {
test(
program: [
0x01, 0x02, 0x00, // LD BC, 2
0xed, 0xb1, // CPIR
0x00, 0x00, 0x00 // NOP, NOP, NOP
],
busCycles: [
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .read, length: 3),
MachineCycle(operation: .internalOperation, length: 5),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
MachineCycle(operation: .readOpcode, length: 4),
]
)
}
} }

2
Processors/Z80/Z80.hpp
View File

@ -534,7 +534,7 @@ template <class T> class Processor {
Instr(4, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r) Instr(4, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r)
InstructionTable base_program_table = { InstructionTable base_program_table = {
/* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16(pc_, bc_)), /* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16Inc(pc_, bc_)),
/* 0x02 LD (BC), A */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)), /* 0x02 LD (BC), A */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)),
/* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */ /* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */